ST7263 datasheet(20/109 Pages) STMICROELECTRONICS

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ST7263

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4 INTERRUPTS AND POWER SAVING MODES

4.1 INTERRUPTS

The ST7 core may be interrupted by one of two dif-

ferent methods: maskable hardware interrupts as

listed in Table 7 Interrupt Mapping and a non-

maskable software interrupt (TRAP). The Interrupt

processing flowchart is shown in Figure 15.

The maskable interrupts must be enabled clearing

the I bit in order to be serviced. However, disabled

interrupts may be latched and processed when

they are enabled (see external interrupts subsec-

tion).

When an interrupt has to be serviced:

– Normal processing is suspended at the end of

the current instruction execution.

– The PC, X, A and CC registers are saved onto

the stack.

– The I bit of the CC register is set to prevent addi-

tional interrupts.

– The PC is then loaded with the interrupt vector of

the interrupt to service and the first instruction of

the interrupt service routine is fetched (refer to

Table 7 Interrupt Mapping for vector addresses).

The interrupt service routine should finish with the

IRET instruction which causes the contents of the

saved registers to be recovered from the stack.

Note: As a consequence of the IRET instruction,

the I bit will be cleared and the main program will

resume.

Priority management

By default, a servicing interrupt can not be inter-

rupted because the I bit is set by hardware enter-

ing in interrupt routine.

In the case several interrupts are simultaneously

pending, a hardware priority defines which one will

be serviced first (see Table 7 Interrupt Mapping).

Non maskable software interrupts

This interrupt is entered when the TRAP instruc-

tion is executed regardless of the state of the I bit.

It will be serviced according to the flowchart on

Figure 15.

Interrupts and Low power mode

All interrupts allow the processor to leave the Wait

low power mode. Only external and specific men-

tioned interrupts allow the processor to leave the

Halt low power mode (refer to the “Exit from HALT“

column in Table 7 Interrupt Mapping).

External interrupts

The pins ITi/PAk and ITj/PBk (i=1,2; j= 5,6; k=4,5)

can generate an interrupt when a rising edge oc-

curs on this pin. Conversely, pins ITl/PAn and ITm/

PBn (l=3,4; m= 7,8; n=6,7) can generate an inter-

rupt when a falling edge occurs on this pin.

Interrupt generation will occur if it is enabled with

the ITiE bit (i=1 to 8) in the ITRFRE register and if

the I bit of the CCR is reset.

Peripheral interrupts

Different peripheral interrupt flags in the status

are active if both.

– The I bit of the CC register is cleared.

– The corresponding enable bit is set in the control

If any of these two conditions is false, the interrupt

is latched and thus remains pending.

Clearing an interrupt request is done by:

– writing “0” to the corresponding bit in the status

– an access to the status register while the flag is

set followed by a read or write of an associated

Notes:

1. The clearing sequence resets the internal latch.

A pending interrupt (i.e. waiting for being enabled)

will therefore be lost if the clear sequence is exe-

cuted.

2. All interrupts allow the processor to leave the

Wait low power mode.

3. Exit from Halt mode may only be triggered by an

External Interrupt on one of the ITi ports (PA4-PA7

and PB4-PB7), an end suspend mode Interrupt

coming from USB peripheral, or a reset.

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