ST7263 datasheet(31/109 Pages) STMICROELECTRONICS

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ST7263

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I/O PORTS (Cont’d)

5.1.7 Register Description

DATA REGISTERS (PxDR)

Port A Data Register (PADR): 0000h

Port B Data Register (PBDR): 0002h

Port C Data Register (PCDR): 0004h

Read /Write

Reset Value Port A: 0000 0000 (00h)

Reset Value Port B: 0000 0000 (00h)

Reset Value Port C: 1111 x000 (FXh)

Note: for Port C, unused bits (7-3) are not acces-

sible.

Bit 7:0 = D7-D0

Data Register 8 bits.

The DR register has a specific behaviour accord-

ing to the selected input/output configuration. Writ-

ing the DR register is always taken in account

even if the pin is configured as an input. Reading

the DR register returns either the DR register latch

content (pin configured as output) or the digital val-

ue applied to the I/O pin (pin configured as input).

DATA DIRECTION REGISTER (PxDDR)

Port A Data Direction Register (PADDR): 0001h

Port B Data Direction Register (PBDDR): 0003h

Port C Data Direction Register (PCDDR): 0005h

Read/Write

Reset Value Port A: 0000 0000 (00h)

Reset Value Port B: 0000 0000 (00h)

Reset Value Port C: 1111 x000 (FXh)

Note: for Port C, unused bits (7-3) are not acces-

sible

Bit 7:0 = DD7-DD0

Data Direction Register 8 bits.

The DDR register gives the input/output direction

configuration of the pins. Each bits is set and

cleared by software.

0: Input mode

1: Output mode

Table 13. I/O Ports Register Map

DD7

DD6

DD5

DD4

DD3

DD2

DD1

DD0

Address

(Hex.)

Label

PADR

MSB

LSB

PADDR

MSB

LSB

PBDR

MSB

LSB

PBDDR

MSB

LSB

PCDR

MSB

LSB

PCDDR

MSB

LSB

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