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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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ST7263 数据表(PDF) 98 Page - STMicroelectronics |
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ST7263 数据表(HTML) 98 Page - STMicroelectronics |
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98 / 109 page  ST7263 98/109 7.6 LOW VOLTAGE DETECTOR (LVD) CHARACTERISTICS 7.7 CONTROL TIMING CHARACTERISTICS (Operating conditions T A = 0 to +70°C unless otherwise specified) Note 1: The minimum period t ILIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 cycles. C LOW VOLTAGE RESET Electrical Specifications Symbol Parameter Conditions Min Typ Max Unit VIT+ Low Voltage Reset Threshold VDD rising VDD Max. Variation 50mV/ µs 3.6 3.75 4.0 V VIT- Low Voltage Reset Threshold VDD falling VDD Max. Variation 50mV/ µs 3.2 3.5 3.7 V Vhys Hysteresis (VIT+ - VIT-) 200 250 mV CONTROL TIMINGS Symbol Parameter Conditions Value Unit Min Typ. Max fOSC Oscillator Frequency 24 MHz fCPU Operating Frequency 8 MHz tRL External RESET Input pulse Width 1.5 tCPU tPORL Internal Power Reset Duration 4096 tCPU TDOGL Watchdog & Low Voltage Reset Output Pulse Width 200 ns tDOG Watchdog Time-out fcpu = 8MHz 49152 6 3145728 384 tCPU ms tOXOV Crystal Oscillator Start-up Time 50 ms tDDR Power up rise time from VDD = 0 to 4V 100 ms |
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