ADE7166 datasheet(44/148 Pages) AD

44 / 148 page

ADE75xx/ADE71xx

Preliminary Technical Data

Rev. PrE | Page 44 of 148

RESERVED

GAIN REGISTER*

CURRENT AND VOLTAGE CHANNELS PGA CONTROL

ADDR:

1BH

* REGISTER CONTENTS

SHOW POWER-ON DEFAULTS

PGA 2 GAIN SELECT

000 = x 1

001 = x 2

010 = x 4

011 = x 8

100 = x 16

PGA 1 GAIN SELECT

000 = x 1

001 = x 2

010 = x 4

011 = x 8

100 = x 16

Figure 17. ADE75XX/ADE71XX Analog Gain Register

ANALOG TO DIGITAL CONVERSION

The ADE75XX/ADE71XX has two sigma-delta Analog to

Digital Converters (ADC). The outputs of these ADCs are

mapped directly to waveform sampling SFRs (address 0xE2 to

0xE7) and are used for the energy measurement internal digital

signal processing. In PSM1 (Battery mode)and PSM2 (Sleep

mode), the ADCs are powered down to minimize power

consumption.

For simplicity, the block diagram in Figure 18 shows a first-

order Σ-Δ ADC. The converter is made up of the Σ-Δ

modulator and the digital low-pass filter.

DIGITAL

LOW-PASS

FILTER

ANALOG

LOW-PASS FILTER

–

VREF

1-BIT DAC

INTEGRATOR

MCLK/5

LATCHED

COMPARATOR

.....10100101.....

–

Figure 18. First-Order

Σ-∆ ADC

A Σ-∆ modulator converts the input signal into a continuous

serial stream of 1s and 0s at a rate determined by the sampling

clock. In the ADE75xx/ADE71xx, the sampling clock is equal to

MCLK/5. The 1-bit DAC in the feedback loop is driven by the

serial data stream. The DAC output is subtracted from the input

signal. If the loop gain is high enough, the average value of the

DAC output (and therefore the bit stream) can approach that of

the input signal level. For any given input value in a single

sampling interval, the data from the 1-bit ADC is virtually

meaningless. Only when a large number of samples are averaged

is a meaningful result obtained. This averaging is carried out in

the second part of the ADC, the digital low-pass filter. By

averaging a large number of bits from the modulator, the low-

pass filter can produce 24-bit data-words that are proportional

to the input signal level.

The Σ-Δ converter uses two techniques to achieve high

resolution from what is essentially a 1-bit conversion technique.

The first is oversampling. Oversampling means that the signal is

sampled at a rate (frequency), which is many times higher than

the bandwidth of interest. For example, the sampling rate in the

ADE75xx/ADE71xx is MCLK/5 (819.2 kHz) and the band of

interest is 40 Hz to 2 kHz. Oversampling has the effect of

spreading the quantization noise (noise due to sampling) over a

wider bandwidth. With the noise spread more thinly over a

wider bandwidth, the quantization noise in the band of interest

is lowered — see Figure 19. However, oversampling alone is not

efficient enough to improve the signal-to-noise ratio (SNR) in

the band of interest. For example, an oversampling ratio of 4 is

required just to increase the SNR by only 6 dB (1 bit). To keep

the oversampling ratio at a reasonable level, it is possible to

shape the quantization noise so that the majority of the noise

lies at the higher frequencies. In the Σ-Δ modulator, the noise is

shaped by the integrator, which has a high-pass-type response

for the quantization noise. The result is that most of the noise is

at the higher frequencies where it can be removed by the digital

low-pass filter. This noise shaping is shown in Figure 19.

409.6

819.2

NOISE

SIGNAL

DIGITAL

FILTER

ANTILALIAS

FILTER (RC)

SAMPLING

FREQUENCY

HIGH RESOLUTION

OUTPUT FROM DIGITAL

LPF

SHAPED

NOISE

409.6

819.2

NOISE

SIGNAL

FREQUENCY (kHz)

02875-0-047

Figure 19. Noise Reduction Due to Oversampling and

Noise Shaping in the Analog Modulator

Anti-aliasing Filter

Figure 18 also shows an analog low-pass filter (RC) on the input

to the modulator. This filter is present to prevent aliasing.

Aliasing is an artifact of all sampled systems. Aliasing means

that frequency components in the input signal to the ADC,

which are higher than half the sampling rate of the ADC,

appear in the sampled signal at a frequency below half the

sampling rate. Figure 20 illustrates the effect. Frequency

components (arrows shown in black) above half the sampling

frequency (also know as the Nyquist frequency, i.e., 409.6 kHz)

are imaged or folded back down below 409.6 kHz. This happens

with all ADCs regardless of the architecture. In the example

shown, only frequencies near the sampling frequency, i.e., 819.2

kHz, move into the band of interest for metering, i.e., 40 Hz to 2

kHz. This allows the use of a very simple LPF (low-pass filter)

to attenuate high frequency (near 819.2 kHz) noise, and

prevents distortion in the band of interest. For conventional

current sensors, a simple RC filter (single-pole LPF) with a

ADE7166 数据表(PDF) 44 Page - Analog Devices

ADE7166 数据表(HTML) 44 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

ADE7166 数据表(PDF) 44 Page - Analog Devices

ADE7166 数据表(HTML) 44 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载