ADE7166 datasheet(98/148 Pages) AD

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Preliminary Technical Data

ADE75xx/ADE71xx

Rev. PrE | Page 98 of 148

LCD SETUP

The LCD Configuration SFR (LCDCON, 0x95) configures the

LCD module to drive the type of LCD in the user end system.

The BIAS and LMUX[1:0] bits in this SFR should be set

according to the LCD specifications.

The COM2/FP28 and COM3/FP27 pins default to LCD

segment lines. Selecting the 3x multiplex level in the LCD

Configuration SFR (LCDCON, 0x95) by setting LMUX[1:0] to

2d, changes the FP28 pin functionality to COM2. The 4x

multiplex level selection, LMUX[1:0]=3d, changes the FP28 pin

to COM2 and the FP27 pin to COM3.

LCD segments FP0-FP15 are enabled by default. Additional

pins are selected for LCD functionality in the LCD Segment

Enable SFR (LCDSEGE, 0x97) and LCD Segment Enable 2 SFR

(LCDSEGE2, 0xED) where there are individual enable bits for

segment pins FP16-25. The LCD pins do not have to be enabled

sequentially. For example, if the alternate function of FP23, the

timer 2 input, is required, then any of the other shared pins,

FP16-25, could be enabled instead.

The Display Element Control section contains details about

setting up the LCD data memory to turn individual LCD

segments ON and OFF. Setting the LCDRST bit in the LCD

Configuration SFR (LCDCON, 0x95) will reset the LCD data

memory to its default, zero. A power on reset also clears the

LCD data memory.

LCD TIMING AND WAVEFORMS

An LCD segment acts like a capacitor that is charged and

discharged at a certain rate. The rate at which these capacitors

are charged and discharged, the refresh rate, determines the

visual characteristics of the LCD. A slow refresh rate will result

in the user being able to see the LCD blink on and off in

between refreshes. A fast refresh rate will present a screen that

appears to be lit up continuously. However, a faster refresh rate

consumes more power.

The frame rate, or refresh rate, for the LCD module is derived

from the LCD clock, fLCDCLK. The LCD clock is selected as

2048Hz or 128Hz by the CLKSEL bit in the LCD Configuration

X SFR (LCDCONX, 0x9C). The minimum refresh rate that is

needed for the LCD to appear solid, without blinking, is

independent of the multiplex level.

The LCD waveform frequency, fLCD, is the frequency at which

the LCD switches which common line is active. Thus the LCD

waveform frequency depends heavily on the multiplex level.

The frame rate and LCD waveform frequency are set by fLCDCLK,

the multiplex level and the FD[3:0] frame rate selection bits in

the LCD Clock SFR (LCDCLK, 0x96).

The LCD module provides 16 different frame rates for

fLCDCLK=2048Hz, ranging from 8 to 128Hz for an LCD with 4x

multiplexing. There are fewer options available with

fLCDCLK=128Hz, ranging from 8 to 32Hz for a 4x multiplexed

LCD. The 128Hz clock is beneficial for battery operation

because it consumes less power than the 2048Hz clock. The

frame rate is set by the FD[3:0] bits in the LCD Clock SFR

(LCDCLK, 0x96)—see Table 79 and Table 80.

The LCD waveform is inverted at twice the LCD waveform

frequency, fLCD. This way each frame has an average DC offset of

zero. ADC offset would degrade the lifetime and performance

of the LCD.

BLINK MODE

Blink mode is enabled by setting the BLINKEN bit in the LCD

Configuration SFR (LCDCON, 0x95). This mode is used to

alternate between LCD on and off states so that the LCD screen

appears to blink. There are two blinking modes: a software

controlled blink mode and an automatic blink mode.

Software Controlled Blink Mode

The LCD blink rate can be controlled by user code with the

BLKMOD[1:0] bits in the LCD Clock SFR (LCDCLK, 0x96) by

toggling the bits to turn the display on and off at a rate

determined by the MCU code.

Automatic Blink Mode

There are five blink rates available if the RTC peripheral is

enabled (enable the RTC by…xxx). These blink rates are

selected by the BLKMOD[1:0] and BLKFREQ[1:0] bits in the

LCD Clock SFR (LCDCLK, 0x96) – see Table 78.

DISPLAY ELEMENT CONTROL

A bank of 15 bytes of data memory located in the LCD module

controls the on or off state of each segment of the LCD. The

LCD data memory is stored in addresses 0 through 14 in the

LCD module. Each byte configures the on and off states of two

segment lines. The LSBs store the state of the even numbered

segment lines and the MSBs store the state of the odd

numbered segment lines. For example, LCD data address zero

refers to segment lines one and zero—see Table 85. Note that

the LCD data memory is maintained in the PSM2 operating

mode.

Table 85. LCD Data Memory accessed indirectly through

LCD Pointer SFR (LCDPTR, 0xAC) and LCD Data SFR

(LCDDAT, 0xAE)

LCD Memory

Address

COM3

COM2

COM1

COM0

COM3

COM2

COM1

COM0

0Eh

FP28

0Dh

FP27

FP26

0Ch

FP25

FP24

0Bh

FP23

FP22

0Ah

FP21

FP20

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