ADE7166 datasheet(86/148 Pages) AD

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ADE75xx/ADE71xx

Preliminary Technical Data

Rev. PrE | Page 86 of 148

Table 66. WatchDog Timer SFR (WDCON, 0xC0)

Bit

Location

Bit

Addr.

Bit

Name

Default

Value

Description

7-4

0xC7 –

0xC4

PRE[3:0]

Watchdog pre-scaler. In normal mode, the 16-bit watchdog timer is clocked by the

input clock (32.768kHz). The PRE bits set which of the upper bits of the counter are

used as the watchdog output following:

CLKIN

PRE

watchdog

[3:0]

Watchdog Timeout

0000

15.6ms

0001

31.2ms

0010

62.5ms

0011

125ms

0100

250ms

0101

500ms

0110

0111

1000

Automatic Reset

1001

Serial download reset

1010 to 1111

Not a valid selection

0xC3

WDIR

Watchdog interrupt response bit.

When clear, watchdog will generate a system reset when the watchdog time out

period has expired

When set, the watchdog will generate a interrupt when the watchdog time out

period has expired.

0xC2

WDS

WDS Watchdog status bit.

This bit is set to indicate that a watchdog timeout has occurred.

WDS is cleared by writing a zero or by an external hardware reset. A watchdog

reset will not clear WDS. The bit can therefore be used to distinguish between a

watchdog reset and a hardware reset from the RESET pin.

0xC1

WDE

WDE Watchdog enable bit.

When set, enables the watchdog and clears its counter (e.g. 2 above). The

watchdog counter is subsequently cleared again whenever the WDE bit is set. If

the watchdog is not cleared within its selected timeout period it will generate a

system reset or watchdog interrupt, depending on the WDIR bit. The watchdog is

disabled (and WDE cleared) by any of the following:

Write zero to WDE

Watchdog reset (WDIR = 0)

Hardware reset

PSM interrupt

LOCK interrupt.

0xC0

WDWR

WDWR Watchdog write enable bit. To write data into the WDCON SFR involves a

double instruction sequence. The WDWR bit must be set and the following

instruction must be a write instruction to the WDCON SFR. This sequence is

necessary so that the WDCON SFR is protected from code execution upsets that

might unintentionally modify this SFR. Interrupts should be disabled during this

operation due to the consecutive instruction cycles.

e.g. Disable Watch dog

1 write to WDCON e.g. 2 Clear WDE bit

CLR EA

SETB WDWR

CLR WDE

SETB EA

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