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ADE75xx/ADE71xx

Preliminary Technical Data

Rev. PrE | Page 64 of 148

∫

Power

Apparent

Energy

Apparent

)

(

(30)

The ADE75XX/ADE71XX achieves the integration of the

apparent power signal by continuously accumulating the

apparent power signal in an internal 48-bit register. The

apparent energy register (VAHR[23:0]) represents the upper 24

bits of this internal register. This discrete time accumulation or

summation is equivalent to integration in continuous time.

Equation 31 expresses the relationship

⎪⎭

⎪

⎬

⎫

⎪⎩

⎪

⎨

⎧

∑

∞

→

)

(

Power

Apparent

Lim

Energy

Apparent

(31)

where:

n is the discrete time sample number.

T is the sample period.

The discrete time sample period (T) for the accumulation

Figure 50 shows this discrete time integration or accumulation.

The apparent power signal is continuously added to the internal

energy remains theoretically always positive.

The 49 bits of the internal register are divided by VADIV. If the

value in the VADIV register is 0, then the internal apparent

energy register is divided by 1. VADIV is an 8-bit unsigned

apparent energy register (VAHR[23:0]). RVAHR register (24

bits long) is provided to read the apparent energy. This register

is reset to 0 after a read operation.

VADIV

APPARENT POWER

VAHR[23:0]

APPARENT POWER ARE

ACCUMULATED (INTEGRATED) IN

THE APPARENT ENERGY REGISTER

TIME (nT)

APPARENT POWER

SIGNAL = P

Figure 50. ADE75XX/ADE71XX Apparent Energy Calculation

Note that the apparent energy register is unsigned. By setting the

VAEHF and VAEOF bits in the Interrupt Enable Register 2 SFR

(MIRQENM, 0xDA), the ADE75XX/ADE71XX can be con-

figured to issue an ADE interrupt to the 8052 core when the

apparent energy register is half full or when an overflow occurs.

The half full interrupt for the unsigned apparent energy register

is based on 24 bits as opposed to 23 bits for the signed active

energy register.

Integration Times under Steady Load

As mentioned in the last section, the discrete time sample

period (T) for the accumulation register is 1.22 μs (5/MCLK).

With full-scale sinusoidal signals on the analog inputs and the

VAGAIN register set to 0x000, the average word value from

apparent power stage is 0x1A36E2—see the section. The

maximum value that can be stored in the apparent energy

word value is added to the internal register, which can store 248

or 0xFFFF,FFFF,FFFF before it overflows. Therefore, the

integration time under these conditions with VADIV = 0 is

calculated as follows:

Time =

055

FFFF

FFFF,

xFFFF,

× 1.22 μs = 199 s = 3.33 min (32)

When VADIV is set to a value different from 0, the integration

time varies, as shown in Equation 33.

Time = TimeWDIV = 0 × VADIV

(33)

Apparent energy Pulse output

ADE75XX/ADE71XX also provides all the circuitry to have a

pulse output those frequency is proportional to apparent power

– see Energy-to-Frequency Conversion section. This pulse

frequency output uses the calibrated signal after VAGAIN. This

output can also be used to output a pulse those frequency is

proportional to Irms.

The pulse output is active low and should be preferably

connected to an LED as shown on Figure 53.

Line Apparent Energy Accumulation

The ADE75XX/ADE71XX is designed with a special apparent

energy accumulation mode, which simplifies the calibration

process.

By using the on-chip zero-crossing detection, the

ADE75XX/ADE71XX accumulates the apparent power signal

in the LVAHR register for an integral number of half cycles, as

shown in Figure 51. The line apparent energy accumulation

mode is always active.

The number of half line cycles is specified in the LINCYC

ADE75XX/ADE71XX can accumulate apparent power for up to

65535 combined half cycles. Because the apparent power is

integrated on the same integral number of line cycles as the line

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