ADE7166 datasheet(88/148 Pages) AD

88 / 148 page

ADE75xx/ADE71xx

Preliminary Technical Data

Rev. PrE | Page 88 of 148

I2CSTAT

I2C Interrupt Status register

TIMECON.7

RTC Midnight flag

IRTC

TIMECON.2

RTC Alarm flag

WDT (Watchdog Timer)

WDCON.2

WDS

Watchdog Timeout flag

A functional block diagram of the interrupt system is shown in

Figure 62. Note that the PSM interrupt is the only interrupt in

the highest priority level.

If an external wakeup event occurs to wake the

ADE75XX/ADE71XX from PSM2, a pending external interrupt

will be generated. When the EX0 or EX1 bits are set in the

Interrupt Enable SFR (IE, 0xA8) to enable external interrupts,

the program counter will be loaded with the IE0 or IE1

interrupt vector. The IE0 and IE1 interrupt flags in the TCON

MCU core is shut down during PSM2 — see the Power Supply

Monitor Interrupt (PSM) section.

The RTC, temperature ADC and I2C/SPI interrupts are latched

such that pending interrupts cannot be cleared without entering

their respective interrupt service routines. Clearing the RTC

Midnight and Alarm flags will not clear a pending RTC

interrupt. Similarly, clearing the I2C/SPI status bits in the SPI

Interrupt Status Register SFR (SPISTAT, 0xEA) will not cancel a

pending I2C/SPI interrupt. These interrupts will remain

pending until the RTC or I2C/SPI interrupt vectors are enabled.

Their respective interrupt service routines will be entered

shortly thereafter.

Figure 62 shows how the interrupts are cleared when the

interrupt service routines are entered. Some interrupts with

multiple interrupt sources are not automatically cleared,

specifically the PSM, ADE, UART and Timer 2 interrupt

vectors. Note that the INT0 and INT1 interrupts are only

cleared if the external interrupt is configured to be triggered by

a falling edge, by setting IT0 in the Timer/Counter 0 and 1

Control SFR (TCON, 0x88). If INT0 or INT1 is configured to

interrupt on a low level, the interrupt service routine will be

reentered until the respective pin goes high.

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