ADE7166 datasheet(73/148 Pages) AD

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Preliminary Technical Data

ADE75xx/ADE71xx

Rev. PrE | Page 73 of 148

8052 MCU CORE ARCHITECTURE

The ADE75XX/ADE71XX has an 8052 MCU core and uses the

8051 instruction set. Some of the standard 8052 peripherals,

such as the UART, have been enhanced. This section describes

the standard 8052 core and enhancements that have been made

to it in the ADE75XX/ADE71XX.

The special function register (SFR) space is mapped into the

upper 128 bytes of internal data memory space and is accessed

by direct addressing only. It provides an interface between the

CPU and all on-chip peripherals. A block diagram showing the

programming model of the ADE75XX/ADE71XX via the SFR

area is shown in Figure 54.

All registers except the program counter (PC), instruction

in the SFR area. The SFR registers include control,

configuration, and data registers that provide an interface

between the CPU and all on-chip peripherals.

OTHER ON-CHIP

PERIPHERALS:

SERIAL I/O

WDT

TIMERS

BATTERY ADC

TEMPERATURE ADC

LCD DRIVER

RTC

POWER MANAGEMENT

ENERGY MEASUREMENT

16-kBYTE

ELECTRICALLY

REPROGRAMMABLE

NONVOLATILE

FLASH/EE PROGRAM/DATA

MEMORY

256 BYTES XRAM

8051

COMPATIBLE

CORE

STACK

BANKS

256 BYTES

GENERAL

PURPOSE

RAM

128-BYTE

SPECIAL

FUNCTION

AREA

Figure 54: ADE75XX/ADE71XX Block Diagram

MCU REGISTERS

The registers used by the MCU are summarized hereafter.

Table 53. 8051 SFRs

SFR

Address

Bit Addressable

Description

0xE0

Yes

Accumulator

0xF0

Yes

Auxiliary Math register

PSW

0xD0

Yes

Program status word - see Table 54

PCON

0x87

Power Control register – see Table 55

DPL

0x82

Data pointer LSByte – see Table 56

DPH

0x83

Data pointer MSbyte – see Table 57

0x81

Stack pointer LSB byte – see Table 58

CFG

0xAF

Configuration register – see Table 59

Table 54. Program Status Word SFR (PSW, 0xD0)

Bit Location

Bit Addr.

Bit Name

Description

0xD7

Carry Flag. Modified by ADD, ADDC, SUBB, MUL, and DIV instructions.

0xD6

Auxiliary Carry Flag. Modified by ADD, and ADDC instructions.

0xD5

General-Purpose Flag availble to the user

RS1

RS0

Selected Bank

4-3

0xD4,

0xD3

RS1, RS0

0xD2

Overflow Flag. Modified by ADD, ADDC, SUBB, MUL and DIV instructions.

0xD1

General-Purpose Flag availble to the user.

0xD0

Parity Bit. The number of bits set in the Accumulator added to the value of the parity bit

will always be an even number.

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