ADE7166 datasheet(84/148 Pages) AD

84 / 148 page

ADE75xx/ADE71xx

Preliminary Technical Data

Rev. PrE | Page 84 of 148

INTERRUPT SYSTEM

The unique power management architecture of the

ADE75XX/ADE71XX includes an operating mode where the

8052 MCU core is shut down, PSM2. There are events that can

be configured to wake the 8052 MCU core from the PSM2

operating mode where the MCU core is shut down. A

distinction is drawn here between events that can trigger the

wakeup of the 8052 MCU core and events that can trigger an

interrupt when the MCU core is active. Events that can wake the

core are referred to as wakeup events while events that can

interrupt the program flow when the MCU is active are called

interrupts

. See the 3.3V Peripherals and Wakeup Events section

to learn more about events that can wake the 8052 core from

PSM2.

The ADE75XX/ADE71XX provides 12 interrupt sources with

three priority levels. The power management interrupt is alone

at the highest priority level. The other two priority levels are

configurable through the Interrupt priority SFR (IP, 0xB8) and

Interrupt Enable and Priority 2 SFR (IEIP2, 0xA9).

STANDARD 8051 INTERRUPT ARCHITECTURE

The 8051 standard interrupt architecture includes two tiers of

interrupts, where some interrupts are assigned a high priority

and others are assigned a low priority.

Priority 0

Priority 1

High

Low

Figure 60: Standard 8051 Interrupt Priority Levels

A Priority 1 interrupt can interrupt the service routine of a

Priority 0 interrupt, and if two interrupts of different priorities

occur at the same time, the Priority 1 interrupt is serviced first.

An interrupt cannot be interrupted by another interrupt of the

same priority level. If two interrupts of the same priority level

occur simultaneously, a polling sequence is observed. See the

Interrupt Priority section.

ADE75XX/ADE71XX INTERRUPT ARCHITECTURE

The ADE75XX/ADE71XX provides advanced power supply

monitoring features. To ensure a fast response to time critical

power supply issues, such as a loss of line power, the power

supply monitoring interrupt should be able to interrupt any

interrupt service routine. In order to enable the user to make

full use of the standard 8051 interrupt priority levels, an

additional priority level was added for the power supply

management, PSM, interrupt. The PSM interrupt is the only

interrupt at this highest interrupt priority level.

Priority 0

Priority 1

PSM

High

Low

Figure 61: ADE75XX/ADE71XX Interrupt Architecture

See the Power Supply Monitor Interrupt (PSM) section for

more information on the PSM interrupt.

INTERRUPT SFR REGISTER LIST

The control and configuration of the interrupt system is carried out through three interrupt-related SFRs:

SFR

Address

Default

Value

Bit

Addressable

Description

0xA8

0x00

Yes

Interrupt Enable Register

0xB8

0x00

Yes

Interrupt Priority Register

IEIP2

0xA9

0xA0

Secondary Interrupt Enable

INTPR

0xFF

0x00

Interrupt Pins Configuration SFR

Table 63. Interrupt Enable SFR (IE, 0xA8)

Bit Location

Bit Addr.

Bit Name

Description

0xAF

Set by the user to enable all interrupt sources.

Cleared by the user to disable all interrupt sources.

0xAE

ETEMP

Set by the user to enable the temperature ADC interrupt.

0xAD

ET2

Set by the user to enable the Timer 2 interrupt.

0xAC

Set by the user to enable the UART serial port interrupt.

0xAB

ET1

Set by the user to enable the Timer 1 interrupt.

0xAA

EX1

Set by the user to enable External Interrupt 1 (INT1).

0xA9

ET0

Set by the user to enable the Timer 0 interrupt.

ADE7166 数据表(PDF) 84 Page - Analog Devices

ADE7166 数据表(HTML) 84 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

ADE7166 数据表(PDF) 84 Page - Analog Devices

ADE7166 数据表(HTML) 84 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载