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ADE75xx/ADE71xx

Preliminary Technical Data

Rev. PrE | Page 56 of 148

well as calculating the energy, this integration removes any

sinusoidal components that might be in the active power signal.

Figure 39 shows this discrete time integration or accumulation.

The active power signal in the waveform register is

continuously added to the internal active energy register.

The Active Energy accumulation depends on the setting of the

POAM and ABSAM bits in the ACCMODE register (0x0F).

When both bits are cleared, the addition is signed and therefore

negative energy is subtracted from the active energy contents.

When both bits are set, the ADE75XX/ADE71XX is set to be in

the more restrictive mode, the Positive Only Accumulation

mode.

When POAM bit in the ACCMODE register (0x0F) is set, only

positive power contributes to the active energy accumulation —

see the Watt positive-only accumulation mode section.

When ABSAM bit in the ACCMODE register (0x0F) is set, the

absolute active power is used for the active energy accumulation

— see the Watt absolute accumulation mode section.

The output of the multiplier is divided by WDIV. If the value in

the WDIV register is equal to 0, then the internal active energy

After dividing by WDIV, the active energy is accumulated in a

49-bit internal energy accumulation register. The upper 24 bits

of this register are accessible through a read to the active energy

returns the content of the WATTHR register and the upper 24

bits of the internal register are cleared. As shown in Figure 39, the

active power signal is accumulated in an internal 49-bit signed

the WFSM bit in the Interrupt Enable Register 3 SFR

(MIRQENH, 0xDB). Like the current and voltage channels

waveform sampling modes, the waveform date is available at

sample rates of 27.9 kSPS, 14 kSPS, 7 kSPS, or

3.5 kSPS.

Figure 40 shows this energy accumulation for full-scale signals

(sinusoidal) on the analog inputs. The three curves displayed

illustrate the minimum period of time it takes the energy register

to roll over when the active power gain register contents are

0x7FF, 0x000, and 0x800. The watt gain register is used to carry

out power calibration in the ADE75XX/ADE71XX. As shown,

the fastest integration time occurs when the watt gain register is

set to maximum full scale, i.e., 0x7FF.

0x00,0000

0x7F,FFFF

0x3F,FFFF

0x40,0000

0x80,0000

WATTHR [23:0]

6.82

3.41

10.2

13.7

TIME (minutes)

WGAIN = 0x7FF

WGAIN = 0x000

WGAIN = 0x800

Figure 40. Energy Register Rollover Time for Full-Scale Power

(Minimum and Maximum Power Gain)

Note that the energy register contents rolls over to full-scale

negative (0x800000) and continues to increase in value when

the power or energy flow is positive—see Figure 40. Conversely,

if the power is negative, the energy register underflows to full-

scale positive (0x7FFFFF) and continues to decrease in value.

By using the interrupt enable register, the ADE75XX/ADE71XX

can be configured to issue an ADE interrupt to the 8052 core

when the active energy register is half-full (positive or negative)

or when an overflow or underflow occurs.

Integration time under steady Load

As mentioned in the last section, the discrete time sample

period (T) for the accumulation register is 1.22 μs (5/CLKIN).

With full-scale sinusoidal signals on the analog inputs and the

WGAIN register set to 0x000, the average word value from each

LPF2 is 0xCCCCD—see Figure 37. The maximum positive

value that can be stored in the internal 49-bit register is 248 or

0xFFFF,FFFF,FFFF before it overflows. The integration time

under these conditions with WDIV = 0 is calculated as follows:

Time =

xCCCCD

FFFF

FFFF,

xFFFF,

× 1.22 μs = 409.6 s = 6.82 min(15)

When WDIV is set to a value different from 0, the integration

time varies, as shown in Equation 16.

WDIV

Time

WDIV

(16)

Active energy accumulation modes

Watt signed accumulation mode

The ADE75XX/ADE71XX active energy default accumulation

mode is a signed accumulation based on the active power

information.

Watt positive-only accumulation mode

The ADE75XX/ADE71XX is placed in positive-only

accumulation mode by setting the POAM bit in the

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