ORSPI4 datasheet(101/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

101

ORSPI4 SPI4 Clocking

Transmit Clocking

The following descriptions and ﬁgures show the SPIA core. The SPIB core is identical.

Figure 45. SPI4 TX Clocking

ATREFCLK: External Pad. Reference clock for the high-speed SPIA transmit block. Its frequency is 1/4th the SPI4

line clock ATDCLK. The ATREFCLK pad should be tied off during quarter-rate mode.

SPIA_TREFCLK_x8: Reference clock source from the FPGA when SPIA is operating in quarter-rate mode. Its fre-

quency is two times the SPI4 line clock. i.e. if SPI4 line clock is 100 MHz, this clock is 200 MHz. Maximum allow-

able frequency is 200 MHz.

ATDCLK[P,N]: External output pads. SPI4 transmit data clock. SPI4 transmit data ATDAT and ATCTL are valid on

both edges of this clock.

ATSCLK[P,N]: External input LVDS pads. SPI4 transmit status clock.

TSCLKA: External input 3.3V LVTTL transmit status input.

SPIA_TXk_CLK_j: Write clocks from FPGA to each of the four asynchronous DPRAMs.

(j = 0, 1, 2 or 3) (k = 32, 64 or 128)

ATREFCLK_F: Clock output to the FPGA. Its frequency is the same as ATREFCLK. It is used to clock the status

outputs to the FPGA, namely SPIA_TXk_PORT_ID, SPIA_TXk_STAT and SPIA_TXk_BURST_VAL.

SPIA TX Status

SPIA TX Core

(Data)

FPGA

SPIA_TXk_CLK_0

SPIA_TXk_CLK_1

SPIA_TXk_CLK_2

SPIA_TXk_CLK_3

SPIA_TREFCLK_x8

ATREFCLK_F

k= 32, 64, or 128

ATREFCLK

ATDCLKP

ATDCLKN

ATSCLKP

ATSCLKN

TSCLKA

LVTTL Input

LVDS Input

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