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ORCA ORSPI4 Data Sheet

105

Backplane Transceiver Core Detailed Description

The following sections describe the various logic blocks in the SERDES portion of the FPSC. For a detailed

description of the programmable logic functions, please see the ORCA Series 4 FPGA Data Sheet and related

application and technical notes.

The major functional blocks in the SERDES include:

• One SERializer-DESerializer (SERDES) block and Clock and Data Recovery (CDR) circuitry

• 8b/10b encoder/decoders

• Transmit pre-emphasis circuitry

• 4-to-1 multiplexers (MUX) and 1-to-4 demultiplexers (DEMUX)

• Fibre channel synchronization state machine

• XAUI link alignment state machine

• Alignment FIFOs

A top level block diagram of the SERDES Logic is shown in Figure 48.

Figure 48. Top Level Block Diagram, SERDES Embedded Core Logic

RCK78

Core

→FPGA Receive low-speed clock to FPGA—SERDES Quad.

RSYS_CLK_1

FPGA

→ Core Low-speed receive FIFO clock for channels A, B

RSYS_CLK_2

FPGA

→ Core Low-speed receive FIFO clock for channels C, D

CV_SELx

FPGA

→ Core Enable detection of code violations in the incoming data

SYS_RST_N

FPGA

→ Core Synchronous reset of the channel alignment blocks.

FPGA_RESET_FC

FPGA

→ Core Disables access to SERDES when high

Logic Common to Quad

Channel B

Channel D

Backplane

Serial

Links

Receive Channel A

2:1 MUX

(x40)

DEMUX

Block

Link State

Machine

RX SER-

DES Block

Multi -

Channel

Alignment

Block

TX SERDES

Block

Interface and

MUX Block

Transmit Channel A

RCK78

TCK78

MRWDA[39:0]

CV_SELA

RWCKA

TSYS_CLK_A

TWDA[31:0]

TCOMMA[3:0]

FPGA

Logic

HDOUT[P:N]_A

HDIN[P:N]_A

REFCLK[P:N]

Channel C

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