ORSPI4 datasheet(104/263 Pages) LATTICE

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ORCA ORSPI4 Data Sheet

104

The SERDES block contains its own dedicated PLLs for both transmit and receive clock generation. The user pro-

vides a reference clock of the appropriate frequency. The receiver PLLs extract the clock from the serial input data

and retime the data with the recovered clock.

MUX/DEMUX Block

The MUX/DEMUX block converts the data format for the high-speed serial links to a wide, low-speed format for

crossing the CORE/FPGA interface. The intermediate interface to the SERDES macrocell runs at 1/10th the bit

rate of the data lane. The MUX/DEMUX converts the data rate and bus width so the interface to the FPGA core can

run at 1/4th this intermediate frequency, giving a range of 25.0-92.5 MHz for the data rates into and out of the

FPGA logic.

Multi-Channel Alignment FIFOs

The four incoming data channels can be independent of each other, or can be synchronized in several ways. Two

channels within a SERDES block can be aligned together; channels A and B and/or channels C and D. Alterna-

tively, four channels in a SERDES block can be aligned together to form a communication channel with a band-

width of 10 Gbits/s.

Individual channels within an alignment group can be disabled (i.e., powered down) without disrupting other chan-

nels.

XAUI and Fibre Channel Link State Machines

Two separate link state machines are included in the architecture. A XAUI link state machine is included in the

SERDES, modeled after the IEEE 802.3ae standard. A separate state machine for Fibre Channel is also imple-

mented.

FPGA/SERDES Interface

In 8b/10b mode, the FPGA logic will receive/transmit 32-bits of data (up to 92.5 MHz) and four K_CTRL bits from/to

the SERDES. There are eight data streams in each direction plus additional timing, status and control signals.

Data sent to the FPGA can be aligned using comma (/K/) characters or the /A/ character as speciﬁed either by

Fibre Channel or by IEEE 802.3ae for XAUI based interfaces. The alignment character is made available to the

FPGA along with the data. The special characters K28.1, K28.5 and K28.7 are treated as valid comma characters

by the SERDES.

If the receive channel alignment FIFOs are bypassed, then each channel will provide its own receive clock in addi-

tion to data and comma character detect signals. If the 8b/10b decoders are bypassed, then 40-bit data streams

are passed to the FPGA logic. No channel alignment can be done in 8b/10b bypass mode.

The following table summarizes the interface signals between the FPGA logic and the core. In the table, an input

refers to a signal ﬂowing into the SERDES and an output refers to a signal ﬂowing out of the SERDES.

Table 26. FPGA/SERDES Interface Description

FPGA/Embedded Core Inter-

face Signal Name

(x = [A, ..,D])

Input (I) to or

Output (O)

from Core

Signal Description

Transmit Path Signals

TWDx[31:0]

FPGA

→ Core Transmit data—channel x.

TCOMMAx[3:0]

FPGA

→ Core Transmit comma character—channel x.

TBIT9x[3:0]

FPGA

→ Core Transmit force negative disparity—channel x

TSYS_CLK_x

FPGA

→ Core Transmit low-speed clock to the FPGA—channel x

TCK78

Core

→FPGA Transmit low-speed clock to the FPGA—SERDES Quad

Receive Path Signals

MRWDx[39:0]

Core

→FPGA Receive data—Channel x (see Table 35).

RWCKx

Core

→FPGA Low-speed receive clock—Channel x.

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