PIN DESCRIPTION

12/51

Release B

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

IOR#, IOW#

I/O

I/O Read and Write

2

MCS16#, IOCS16#

I

Memory/IO Chip Select16

2

BHE#

O

System Bus High Enable

1

ZWS#

I

Zero Wait State

1

REF#

O

Refresh Cycle.

1

MASTER#

I

Add On Card Owns Bus

1

AEN

O

Address Enable

1

IOCHCK#

I

I/O Channel Check.

1

IOCHRDY

I/O

I/O Channel Ready (ISA) - Busy/Ready (IDE)

1

ISAOE#

O

ISA/IDE Selection

1

GPIOCS#

I/O

General Purpose Chip Select

1

IRQ_MUX[3:0]

I

Time-Multiplexed Interrupt Request

4

DREQ_MUX[1:0]

I

Time-Multiplexed DMA Request

2

DACK_ENC[2:0]

O

Encoded DMA Acknowledge

3

TC

O

ISA Terminal Count

1

RTCAS

O

Real Time Clock Address Strobe

1

RMRTCCS#

I/O

ROM/RTC Chip Select

1

KBCS#

I/O

Keyboard Chip Select

1

RTCRW#

I/O

RTC Read/Write

1

RTCDS

I/O

RTC Data Strobe

1

LOCAL BUS

PA[21:0]

O

Address Bus

22

PD[15:0]

I/O

Data Bus

16

PRD1#,PRD0#

O

Peripheral Read Control

2

PWR1#,PWR0#

O

Peripheral Write Control

2

PRDY#

I

Data Ready

1

FCS1#, FCS0#

O

Flash Chip Select

2

IOCS#[3:0]

O

I/O Chip Select

4

IDE CONTROL

DA[2:0]

O

Address Bus

3

DD[15:0]

I/O

Data Bus

16

PCS3#,PCS1#,SCS3#,SCS1#

O

Primary & Secondary Chip Selects

4

DIORDY

O

Data I/O Ready

1

PIRQ, SIRQ

I

Primary & Secondary Interrupt Request

2

PDRQ, SDRQ

I

Primary & Secondary DMA Request

2

PDACK#, SDACK#

O

Primary & Secondary DMA Acknowledge

2

PDIOR#, SDIOR#

O

Primary & Secondary I/O Channel Read

2

PDIOW#, SDIOW#

O

Primary & Secondary I/O Channel Write

2

MONITOR INTERFACE

RED, GREEN, BLUE

O

Analog Red, Green, Blue

3

VSYNC

O

Vertical Sync

1

HSYNC

O

Horizontal Sync

1

VREF_DAC

I

DAC Voltage reference

1

RSET

I

Resistor Set

1

COMP

I

Compensation

1

Table 2.2. Definition of Signal Pins

Signal Name

Dir

Description

Qty