BOARD LAYOUT

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Release B

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

6.3.3 Board Layout Issues

The physical layout of the motherboard PCB as-

sumed in this presentation is as shown in Figure

6-10. Because all the memory interface signal

balls are located in the same region of the STPC

device it is possible to orientate the device to re-

duce the trace lengths. The worst case routing

length to the DIMM1 is estimated to be 100mm.

Solid power and ground planes are a must in order

to provide good return paths for the signals and to

reduce EMI and noise. Also there should be ample

high frequency decoupling between the power

and ground planes to provide a low impedance

path between the planes for the return paths for

signal routings which change layers. If possible

the traces should be routed adjacent to the same

power or ground plane for the length of the trace.

For the SDRAM interface the most critical signal is

the clock. Any skew between the clocks at the

SDRAM components and the memory controller

will impact the timing budget. In order to get well

matched clocks at all the components it is recom-

mended that all the DIMM clock pins, STPC mem-

ory clock input (MCLKI) and any other component

using the memory clock are individually driven

from a low skew clock driver with matched routing

lengths. This is shown in Figure 6-11.

The maximum skew between pins for this part is

250ps. The important factors for the clock buffer

are a consistent drive strength and low skew be-

tween the outputs. The delay through the buffer is

not important so it does not have to be a zero de-

lay pll type buffer. The trace lengths from the clock

driver to the DIMM CKn pins should be matched

exactly. Since the propagation speed can vary be-

tween PCB layers the clocks should be routed in a

consistent way. The routing to the STPC memory

input should be longer by 75mm to compensate

for the extra clock routing on the DIMM. Also a

20pF capacitor should be placed as near as pos-

sible to the clock input of the STPC to compensate

for the DIMM’s higher clock load. The impedance

of the trace used for the clock routing should be

matched to the DIMM clock trace impedance (60-

75W

be routed with spacing to adjacent tracks of at

least twice the clock trace width. For designs

which use SDRAMs directly mounted on the moth-

erboard PCB all the clock trace lengths should be

matched exactly.

The DIMM sockets should be populated starting

with the furthest DIMM from the STPC device first

(DIMM1). There are 2 types of DIMM devices; sin-

gle row and dual row. The dual row devices re-

quire 2 chip select signals to select between the

two rows. A STPC device with 4 chip select control

lines could control either 4 single row DIMMs or 2

dual row DIMMs.

Figure 6-10. DIMM placement

DIMM4

DIMM3

DIMM2

DIMM1

STPC

35mm

35mm

15mm

10mm

116mm

SDRAMI/F