BOARD LAYOUT

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Release B

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

6.3 Memory interface

6.3.1 Introduction

In order to achieve SDRAM memory interfaces

which work at clock frequencies of 66MHz and

above, careful consideration has to be given to the

timing of the interface with all the various electrical

and physical constraints taken into consideration.

The guidelines described below are related to

SDRAM components on DIMM modules. For ap-

plications where the memories are directly sol-

dered to the motherboard, the PCB should be laid

out such that the trace lengths fit within the con-

straints shown here. The traces could be slightly

longer since the extra routing on the DIMM PCB is

no longer present but it is then up to the user to

verify the timings.

6.3.2 SDRAM Clocking Scheme

The SDRAM Clocking Scheme deserves a special

mention here. Basically the memory clock is gen-

erated on-chip through a PLL and goes directly to

the MCLKO output pin of the STPC. The nominal

frequency is 66MHz. Because of the high load

presented to the MCLK on the board by the

DIMMs it is recommeded to rebuffer the MCLKO

signal on the board and balance the skew to the

clock ports of the different DIMMs and the MCLKI

input pin of STPC.

Figure 6-9. Clock scheme

MCLKI

MCLKO

PLL

PLL

MA[] +Control

MD[]