ELECTRICAL SPECIFICATIONS

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Release B

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

Table 4.4. PCI Bus AC Timing

Name

Parameter

Min

Max

Unit

t1

PCI_CLKI to AD[31:0] valid

2

11

ns

t2

PCI_CLKI to FRAME# valid

2

11

ns

t3

PCI_CLKI to CBE#[3:0] valid

2

11

ns

t4

PCI_CLKI to PAR valid

2

11

ns

t5

PCI_CLKI to TRDY# valid

2

11

ns

T6

PCI_CLKI to IRDY# valid

2

11

ns

T7

PCI_CLKI to STOP# valid

2

11

ns

T8

PCI_CLKI to DEVSEL# valid

2

11

ns

T9

PCI_CLKI to PCI_GNT# valid

2

12

ns

t10

AD[31:0] bus setup to PCI_CLKI

7

ns

t11

AD[31:0] bus hold from PCI_CLKI

0

ns

t12

PCI_REQ#[2:0] setup to PCI_CLKI

10

ns

t13

PCI_REQ#[2:0] hold from PCI_CLKI

0

ns

t14

CBE#[3:0] setup to PCI_CLKI

7

ns

t15

CBE#[3:0] hold to PCI_CLKI

0

ns

t16

IRDY# setup to PCI_CLKI

7

ns

t17

IRDY# hold to PCI_CLKI

0

ns

t18

FRAME# setup to PCI_CLKI

7

ns

t19

FRAME# hold from PCI_CLKI

0

ns

Table 4.5. IDE Bus AC Timing

Name

Parameter

Min

Max

Unit

t20

DD[15:0] setup to PIOR#/SIOR# falling

15

ns

t21

DD[15:0} hold to PIOR#/SIOR# falling

12

ns

Table 4.6. SDRAM Bus AC Timing

Name

Parameter

Min

Max

Unit

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns