PIN DESCRIPTION

13/51

Release B

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

2.2 SIGNAL DESCRIPTIONS

2.2.1 BASIC CLOCKS AND RESETS

SYSRSTI#

System Reset/Power good. This input

is low when the reset switch is depressed. Other-

wise, it reflects the power supply’s power good

signal. This input is asynchronous to all clocks,

and acts as a negative active reset. The reset cir-

cuit initiates a hard reset on the rising edge of this

signal.

SYSRSTO#

Reset Output to System. This is the

system reset signal and is used to reset the rest of

the components (not on Host bus) in the system.

The ISA bus reset is an externally inverted buff-

ered version of this output and the PCI bus reset is

an externally buffered version of this output.

XTALI

14.3MHz Crystal Input

XTALO

14.3MHz Crystal Output. These pins are

connected to the 14.318 MHz crystal to provide

the reference clock for the internal frequency syn-

thesizer to generate all the other clocks.

A 14.318 MHz Series Cut Crystal should be con-

nected between these two pins. Balance capaci-

tors of 15 pF should also be added. In the event of

an external quarzt oscillator providing the master

clock signal to the STPC Consumer-S device, the

TTL signal should be provided on XTALO.

HCLK

Host Clock. This clock supplies the CPU

and the host related blocks. This clock can e dou-

bled inside the CPU and is intended to operate in

the range of 25 to 100 MHz. This clock in generat-

ed internally from a PLL but can be driven directly

from the external system.

DCLK

Dot Clock / Pixel clock. This clock supplies

the display controller, the video pipeline, the ram-

dac, and the TV output logic. Its value is depend-

ent on the selected display mode.

Its frequency can be as high as 135 MHz. This sig-

nal is either driven by the internal PLL either by an

external oscillator. The direction can be controlled

by a strap option or an internal register bit.

DEV_CLK

24MHz Peripheral Clock. This 24MHZ

signal is provided as a convenience for the system

integration of a Floppy Disk driver function in an

external chip.

VIDEO INPUT

VCLK

I

27-33MHz Video Input Port Clock

1

VIN

I

CCIR 601 or 656 YUV Video Data Input

8

VCS

I/O

Composite Synch or Horizontal line SYNC output

1

ODD_EVEN

I/O

Frame Synchronisation

1

ANALOG TV OUTPUT

RED_TV, GREEN_TV, BLUE_TV

O

Analog RGB or S-VHS outputs

3

CVBS

O

Analog video composite output

1

IREF1_TV

I

Reference current of 9bit DAC for CVBS

1

VREF1_TV

I

Reference voltage of 9bit DAC for CVBS

1

IREF2_TV

I

Reference current of 8bit DAC for R,G,B

1

VREF2_TV

I

Reference voltage of 8bit DAC for R,G,B

1

VSSA_TV

I

Analog Vss for DAC

1

VDDA_TV

I

Analog Vdd for DAC

1

MISCELLANEOUS

SPKRD

O

Speaker Device Output

1

SCL

I/O

I C Interface - Clock / Can be used for VGA DDC[1] signal

1

SDA

I/O

I C Interface - Data / Can be used for VGA DDC[0] signal

1

SCAN_ENABLE

I

Reserved (Test pin)

1

Table 2.2. Definition of Signal Pins

Signal Name

Dir

Description

Qty