STPC CONSUMER-S

3/51

Release B

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

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PCI Controller

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Fully compliant with PCI 2.1 specification.

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Integrated PCI arbitration interface. Up to 3

masters can connect directly. External PAL

allows for greater than 3 masters.

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Translation of PCI cycles to ISA bus.

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Translation of ISA master initiated cycle to

PCI.

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Support for burst read/write from PCI master.

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PCI clock is 1/3 or 1/2 Host clock .

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ISA master/slave controller

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Generates the ISA clock from either

14.318MHz oscillator clock or PCI clock

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Supports programmable extra wait state for

ISA cycles

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Supports I/O recovery time for back to back I/

O cycles.

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Fast Gate A20 and Fast reset.

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Supports the single ROM that C, D, or E.

blocks shares with F block BIOS ROM.

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Supports flash ROM.

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Supports ISA hidden refresh.

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Buffered DMA & ISA master cycles to reduce

bandwidth utilization of the PCI and Host bus.

NSP compliant.

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Integrated Peripheral Controller

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2X8237/AT compatible 7-channel DMA

controller.

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2X8259/AT compatible interrupt Controller.

16 interrupt inputs - ISA and PCI.

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Three 8254 compatible Timer/Counters.

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Co-processor error support logic.

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Supports external RTC.

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Local Bus interface

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Multiplxed with ISA interface.

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Low latency bus

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22-bit address bus.

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16-bit data bus with word steering capability.

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Programmable timing (Host clock granularity)

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2 Programmable Flash Chip Select.

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5 Programmable I/O Chip Select.

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Supports 32-bit Flash burst.

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2-level hardware key protection for Flash boot

block protection.

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Supports 2 banks of 8MB flash devices with

boot block shadowed to 0x000F0000.

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IDE Interface

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Supports PIO and Bus Master IDE

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Supports up to Mode 5 Timings

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Transfer Rates to 22 MBytes/sec

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Supports up to 4 IDE devices

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Concurrent channel operation (PIO & DMA

modes) - 4 x 32-Bit Buffer FIFO per channel

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Support for PIO mode 3 & 4.

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Support for DMA mode 1 & 2.

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Support for 11.1/16.6 MB/s, I/O Channel

Ready PIO data transfers.

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Supports 13.3/16.6 MB/s DMA data transfers

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Bus Master with scatter/gather capability

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Multi-word DMA support for fast IDE drives

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Individual drive timing for all four IDE devices

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Supports both legacy & native IDE modes

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Supports hard drives larger than 528MB

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Support for CD-ROM and tape peripherals

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Backward compatibility with IDE (ATA-1).

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Power Management

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Four power saving modes: On, Doze,

Standby, Suspend.

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Programmable system activity detector

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Supports SMM.

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Supports STOPCLK.

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Supports IO trap & restart.

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Independent peripheral time-out timer to

monitor hard disk, serial & parallel ports.

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Supports RTC, interrupts and DMAs wake-up