PIN DESCRIPTION

14/51

Release B

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

2.2.2 MEMORY INTERFACE

MCLKO

Memory Clock Output. This clock is driv-

ing the DIMMs on board and is generated from an

internal PLL. The default value is 66MHz.

MCLKI

Memory Clock Input. This clock is driving

the SDRAM controller, the graphics engine and

display controller. This input should be a buffered

version of the MCLKO signal with the track lengths

between the buffer and the pin matched with the

track lengths between the buffer and the DIMMs.

CS#[3:0]

Chip Select These signals are used to

disable or enable device operation by masking or

enabling all SDRAM inputs except MCLK, CKE,

and DQM.

MA[11:0]

Memory Address. Multiplexed row and

column address lines.

MD[63:0]

Memory Data. This is the 64-bit memory

data bus. MD[40-0] are read by the device strap

option registers during rising edge of SYSRSTI#.

RAS#[1:0]

Row Address Strobe. These signals

enable row access and precharge. Row address

is latched on rising edge of MCLK when RAS# is

low.

CAS#[1:0]

Column Address Strobe. These sig-

nals enable column access. Column address is

latched on rising edge of MCLK when CAS# is

low.

MWE#

Write Enable. Write enable specifies

whether the memory access is a read (MWE# = H)

or a write (MWE# = L).

DQM#[7:0]

Data Mask. Makes data output Hi-Z

after the clock and masks the SDRAM outputs.

Blocks SDRAM data input when DQM active.

2.2.3 PCI INTERFACE

PCI_CLKI

33MHz PCI Input Clock. This signal is

the PCI bus clock input and should be driven from

the PCI_CLKO pin.

PCI_CLKO

33MHz PCI Output Clock. This is the

master PCI bus clock output.

AD[31:0]

PCI Address/Data. This is the 32-bit

multiplexed address and data bus of the PCI. This

bus is driven by the master during the address

phase and data phase of write transactions. It is

driven by the target during data phase of read

transactions.

CBE#[3:0]

Bus Commands/Byte Enables. These

are the multiplexed command and byte enable

signals of the PCI bus. During the address phase

they define the command and during the data

phase they carry the byte enable information.

These pins are inputs when a PCI master other

than the STPC Consumer-S owns the bus and

outputs when the STPC Consumer-S owns the

bus.

FRAME#

Cycle Frame. This is the frame signal of

the PCI bus. It is an input when a PCI master owns

the bus and is an output when STPC Consumer-S

owns the PCI bus.

IRDY#

Initiator Ready. This is the initiator ready

signal of the PCI bus. It is used as an output when

the STPC Consumer-S initiates a bus cycle on the

PCI bus. It is used as an input during the PCI cy-

cles targeted to the STPC Consumer-S to deter-

mine when the current PCI master is ready to

complete the current transaction.

TRDY#

Target Ready. This is the target ready sig-

nal of the PCI bus. It is driven as an output when

the STPC Consumer-S is the target of the current

bus transaction. It is used as an input when STPC

Consumer-S initiates a cycle on the PCI bus.

LOCK#

PCI Lock. This is the lock signal of the PCI

bus and is used to implement the exclusive bus

operations when acting as a PCI target agent.