M32CSLASH86 datasheet(343/505 Pages) RENESAS

343 / 505 page

Page 320

23. CAN Module

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NOTES:

1. Change the BASICCAN bit setting only when the STATE_RESET bit is set to "1" (CAN module

reset completed).

2. The message slot 14 is the first slot to become active after the RESET1 and RESET0 bits are

set to "0".

3. The message slots 0 to 13 are not affected by entering BasicCAN mode.

23.1.1.4 TSPRE1, TSPRE0 Bits

The TSPRE1 and TSPRE0 bits determine which count source is used for the time stamp counter.

NOTES:

1. Change the TSPRE1 and TSPRE0 bit settings only when the STATE_RESET bit is set to "1"

(CAN module reset completed).

23.1.1.5 TSRESET Bit

When the TSRESET bit is set to "1", the CiTSR register is set to "000016". The TSRESET bit is

automatically set to "0" after the CiTSR register is set to "000016".

23.1.1.6 ECRESET Bit

When the ECRESET bit is set to "1", the CiTEC and CiREC registers are set to "0016". The CAN

module forcibly goes into an error active state.

The ECRESET bit is automatically set to "0" after the CAN module enters an error active state.

NOTES:

1. In an error active state, the CAN module is ready to communicate when 11 continuous reces-

sive bits are detected on the CAN bus.

2. The CANiOUT pin provides an "H" signal output as soon as the ECRESET bit is set to "1". The

CAN bus error may occur when setting the ECRESET bit to "1" during CAN frame transmission.

M32C/86 数据表(PDF) 343 Page - Renesas Technology Corp