M32CSLASH86 datasheet(131/505 Pages) RENESAS

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Page 108

11. Interrupts

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11.6.3 Interrupt Sequence

The interrupt sequence is performed between an interrupt request acknowledgment and interrupt routine

execution.

When an interrupt request is generated while an instruction is executed, the CPU determines its interrupt

priority level after the instruction is completed. The CPU starts the interrupt sequence from the following

cycle. However, in regards to the SCMPU, SIN, SMOVB, SMOVF, SMOVU, SSTR, SOUT or RMPA

instruction, if an interrupt request is generated while executing the instruction, the microcomputer sus-

pends the instruction to start the interrupt sequence.

The interrupt sequence is performed as follows:

(1) The CPU obtains interrupt information (interrupt number and interrupt request level) by reading

address 00000016 (address 00000216 for the high-speed interrupt). Then, the IR bit applicable to

the interrupt information is set to "0" (interrupt requested).

(2) The FLG register, prior to an interrupt sequence, is saved to a temporary register(1) within the CPU.

(3) Each bit in the FLG register is set as follows:

• The I flag is set to "0" (interrupt disabled)

• The D flag is set to "0" (single-step disabled)

• The U flag is set to "0" (ISP selected)

(4) A temporary register within the CPU is saved to the stack; or to the SVF register for the high-speed

interrupt.

(5) PC is saved to the stack; or to the SVP register for the high-speed interrupt.

(6) The interrupt priority level of the acknowledged interrupt is set in IPL .

(7) A relocatable vector corresponding to the acknowledged interrupt is stored into PC.

After the interrupt sequence is completed, an instruction is executed from the starting address of the

interrupt routine.

NOTES:

1. Temporary register cannot be modified by users.

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