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H8/3028F 数据表(PDF) 36 Page - Renesas Technology Corp |
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H8/3028F 数据表(HTML) 36 Page - Renesas Technology Corp |
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36 / 923 page ![]() Rev. 2.00, 09/03, page 6 of 890 1.2 Block Diagram Figure 1.1 shows an internal block diagram. Port 3 Port 4 P5 /A P5 /A P5 /A P5 /A 3 2 1 0 19 18 17 16 P2 /A P2 /A P2 /A P2 /A P2 /A P2 /A P2 /A P2 /A 7 6 5 4 3 2 1 0 P9 /SCK /IRQ P9 /SCK /IRQ P9 /RxD P9 /RxD P9 /TxD P9 /TxD 5 4 3 2 1 0 1 0 1 0 1 0 5 4 Port 7 Port A CS0/P84 ADTRG/CS1/IRQ3/P83 CS2/IRQ2/P82 CS3/IRQ1/P81 RFSH/IRQ0/P80 MD MD MD EXTAL XTAL STBY RES NMI 2 1 0 H8/300H CPU Interrupt controller ROM (mask ROM or flash memory) DMA controller (DMAC) Serial communication interface (SCI) 3 channels × Watchdog timer (WDT) Address bus Data bus (upper) Data bus (lower) 15 14 13 12 11 10 9 8 P1 /A P1 /A P1 /A P1 /A P1 /A P1 /A P1 /A P1 /A 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 φ/P67 LWR/P66 HWR/P65 RD/P64 AS/P63 BACK/P62 BREQ/P61 WAIT/P60 RAM 16-bit timer unit 8-bit timer unit A/D converter D/A converter Programmable timing pattern controller (TPC) Port B RESO/FWE* Note: * Functions as RESO in mask ROM version and as FWE in flash memory version. Figure 1.1 Block Diagram |
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