H8SLASH3028F datasheet(21/923 Pages) RENESAS

21 / 923 page

Rev. 2.00, 09/03, page xxi of xxx

7.1.3

Functional Overview ............................................................................................ 191

7.1.4

Input/Output Pins ................................................................................................. 192

7.1.5

7.2

7.2.1

Memory Address Registers (MAR)...................................................................... 194

7.2.2

I/O Address Registers (IOAR) ............................................................................. 195

7.2.3

Execute Transfer Count Registers (ETCR) .......................................................... 195

7.2.4

Data Transfer Control Registers (DTCR)............................................................. 197

7.3

7.3.1

Memory Address Registers (MAR)...................................................................... 200

7.3.2

I/O Address Registers (IOAR) ............................................................................. 200

7.3.3

Execute Transfer Count Registers (ETCR) .......................................................... 201

7.3.4

Data Transfer Control Registers (DTCR)............................................................. 203

7.4

Operation........................................................................................................................... 209

7.4.1

Overview .............................................................................................................. 209

7.4.2

I/O Mode .............................................................................................................. 211

7.4.3

Idle Mode ............................................................................................................. 213

7.4.4

Repeat Mode ........................................................................................................ 216

7.4.5

Normal Mode ....................................................................................................... 219

7.4.6

Block Transfer Mode ........................................................................................... 222

7.4.7

DMAC Activation ................................................................................................ 227

7.4.8

DMAC Bus Cycle ................................................................................................ 229

7.4.9

Multiple-Channel Operation................................................................................. 235

7.4.10 External Bus Requests, DRAM Interface, and DMAC ........................................ 236

7.4.11 NMI Interrupts and DMAC.................................................................................. 237

7.4.12 Aborting a DMAC Transfer ................................................................................. 238

7.4.13 Exiting Full Address Mode .................................................................................. 239

7.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode.......................... 240

7.5

Interrupts ........................................................................................................................... 241

7.6

Usage Notes....................................................................................................................... 242

7.6.1

Note on Word Data Transfer ................................................................................ 242

7.6.2

DMAC Self-Access.............................................................................................. 242

7.6.3

Longword Access to Memory Address Registers ................................................ 242

7.6.4

Note on Full Address Mode Setup ....................................................................... 242

7.6.5

Note on Activating DMAC by Internal Interrupts................................................ 243

7.6.6

NMI Interrupts and Block Transfer Mode............................................................ 244

7.6.7

Memory and I/O Address Register Values........................................................... 244

7.6.8

Bus Cycle when Transfer is Aborted.................................................................... 245

7.6.9

Transfer Requests by A/D Converter ................................................................... 245

Section 8 I/O Ports............................................................................................................... 247

8.1

Overview ........................................................................................................................... 247

8.2

Port 1 ................................................................................................................................. 250

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