H8SLASH3028F datasheet(81/923 Pages) RENESAS

81 / 923 page

Rev. 2.00, 09/03, page 51 of 890

2.8.5

Bus-Released State

In this state the bus is released to a bus master other than the CPU, in response to a bus request.

The bus masters other than the CPU are the DMA controller, the DRAM interface, and an external

bus master. While the bus is released, the CPU halts except for internal operations. Interrupt

requests are not accepted. For details see section 6.10, Bus Arbiter.

2.8.6

Reset State

When the

RES input goes low all current processing stops and the CPU enters the reset state. The I

bit in the condition code register is set to 1 by a reset. All interrupts are masked in the reset state.

Reset exception handling starts when the

RES signal changes from low to high.

The reset state can also be entered by a watchdog timer overflow. For details see section 12,

Watchdog Timer.

2.8.7

Power-Down State

In the power-down state the CPU stops operating to conserve power. There are three modes: sleep

mode, software standby mode, and hardware standby mode.

Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the

SSBY bit is cleared to 0 in the system control register (SYSCR). CPU operations stop

immediately after execution of the SLEEP instruction, but the contents of CPU registers are

retained.

Software Standby Mode: A transition to software standby mode is made if the SLEEP

instruction is executed while the SSBY bit is set to 1 in SYSCR. The CPU and clock halt and all

on-chip supporting modules stop operating. The on-chip supporting modules are reset, but as long

as a specified voltage is supplied the contents of CPU registers and on-chip RAM are retained.

The I/O ports also remain in their existing states.

Hardware Standby Mode: A transition to hardware standby mode is made when the

STBY input

goes low. As in software standby mode, the CPU and all clocks halt and the on-chip supporting

modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are

retained.

For further information see section 20, Power-Down State.

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