H8SLASH3028F datasheet(91/923 Pages) RENESAS

91 / 923 page

Rev. 2.00, 09/03, page 61 of 890

3.4.4

Mode 4

Ports 1, 2, and 5 and part of port A function as address pins A23 to A0, permitting access to a

maximum 16-Mbyte address space. The initial bus mode after a reset is 16 bits, with 16-bit access

to all areas. If all areas are designated for 8-bit access in ABWCR, the bus mode switches to

8 bits. A23 to A21 are valid when 0 is written in bits 7 to 5 of BRCR. (In this mode A20 is always

used for address output.)

3.4.5

Mode 5

Ports 1, 2, and 5 and part of port A can function as address pins A23 to A0, permitting access to a

maximum 16-Mbyte address space, but following a reset they are input ports. To use ports 1, 2,

and 5 as an address bus, the corresponding bits in their data direction registers (P1DDR, P2DDR,

and P5DDR) must be set to 1. For A23 to A20 output, write 0 in bits 7 to 4 of BRCR. The initial bus

mode after a reset is 8 bits, with 8-bit access to all areas. If at least one area is designated for 16-

bit access in ABWCR, the bus mode switches to 16 bits.

3.4.6

Mode 6

This mode operates using the on-chip ROM, RAM, and registers. All I/O ports are available.

Mode 6 supports a maximum address space of 64 kbytes.

3.4.7

Mode 7

This mode operates using the on-chip ROM, RAM, and registers. All I/O ports are available.

Mode 7 supports a 1-Mbyte address space.

H8/3028F 数据表(PDF) 91 Page - Renesas Technology Corp