H8SLASH3028F datasheet(28/923 Pages) RENESAS

28 / 923 page

Rev. 2.00, 09/03, page xxviii of xxx

18.6.3 Erase Mode........................................................................................................... 606

18.6.4 Erase-Verify Mode............................................................................................... 606

18.7 Flash Memory Protection .................................................................................................. 608

18.7.1 Hardware Protection............................................................................................. 608

18.7.2 Software Protection .............................................................................................. 609

18.7.3 Error Protection .................................................................................................... 609

18.8 Flash Memory Emulation in RAM.................................................................................... 612

18.9 NMI Input Disabling Conditions....................................................................................... 614

18.10 Flash Memory PROM Mode ............................................................................................. 615

18.10.1 Socket Adapters and Memory Map ...................................................................... 615

18.10.2 Notes on Use of PROM Mode.............................................................................. 616

18.11 Flash Memory Programming and Erasing Precautions ..................................................... 616

18.12 Mask ROM Overview ....................................................................................................... 622

18.12.1 Block Diagram ..................................................................................................... 622

18.13 Notes on Ordering Mask ROM Version............................................................................ 623

18.14 Notes on Switching from F-ZTAT Version to Mask ROM Version ................................. 624

Section 19 Clock Pulse Generator................................................................................... 625

19.1 Overview ........................................................................................................................... 625

19.1.1 Block Diagram ..................................................................................................... 625

19.2 Oscillator Circuit ............................................................................................................... 626

19.2.1 Connecting a Crystal Resonator ........................................................................... 626

19.2.2 External Clock Input ............................................................................................ 628

19.3 Duty Adjustment Circuit ................................................................................................... 630

19.4 Prescalers........................................................................................................................... 630

19.5 Frequency Divider............................................................................................................. 630

19.5.1 Register Configuration ......................................................................................... 631

19.5.2 Division Control Register (DIVCR)..................................................................... 631

19.5.3 Usage Notes.......................................................................................................... 632

Section 20 Power-Down State.......................................................................................... 633

20.1 Overview ........................................................................................................................... 633

20.2 Register Configuration ...................................................................................................... 635

20.2.1 System Control Register (SYSCR) ...................................................................... 635

20.2.2 Module Standby Control Register H (MSTCRH) ................................................ 637

20.2.3 Module Standby Control Register L (MSTCRL) ................................................. 638

20.3 Sleep Mode........................................................................................................................ 640

20.3.1 Transition to Sleep Mode ..................................................................................... 640

20.3.2 Exit from Sleep Mode .......................................................................................... 640

20.4 Software Standby Mode .................................................................................................... 641

20.4.1 Transition to Software Standby Mode.................................................................. 641

20.4.2 Exit from Software Standby Mode....................................................................... 641

20.4.3 Selection of Waiting Time for Exit from Software Standby Mode...................... 642

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