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H8/3028F 数据表(PDF) 32 Page - Renesas Technology Corp |
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H8/3028F 数据表(HTML) 32 Page - Renesas Technology Corp |
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32 / 923 page ![]() Rev. 2.00, 09/03, page 2 of 890 Table 1.1 Features Feature Description CPU Upward-compatible with the H8/300 CPU at the object-code level General-register machine • Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) High-speed operation • Maximum clock rate: 25 MHz • Add/subtract: 80 ns • Multiply/divide: 560 ns 16-Mbyte address space Instruction features • 8/16/32-bit data transfer, arithmetic, and logic instructions • Signed and unsigned multiply instructions (8 bits x 8 bits, 16 bits x 16 bits) • Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16 bits) • Bit accumulator function • Bit manipulation instructions with register-indirect specification of bit positions Memory H8/3028 Group • ROM: 384 kbytes • RAM: 16 kbytes Interrupt controller • Seven external interrupt pins: NMI, IRQ0 to IRQ5 • 36 internal interrupts • Three selectable interrupt priority levels |
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