H8SLASH3028F datasheet(13/923 Pages) RENESAS

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Rev. 2.00, 09/03, page xiii of xxx

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Table 21.5 Control

Signal Timing

653

Conditions amended

Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VREF = 3.0 V to

AVCC, VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular

specifications), Ta = –40°C to +85°C (wide-range

specifications)

Table amended

RESO output delay time

tRESO

—

100

Table 21.6 Bus Timing 654,

655

Conditions amended

Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VREF = 3.0 V to

AVCC, VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular

specifications), Ta = –40°C to +85°C (wide-range

specifications)

Table amended

RAS precharge

time

tRP

1.5 tcyc – 25

—

Figure 21.17 to

figure 21.19

CAS precharge

time

tCP

0.5 tcyc – 15

—

Row address hold

time

tRAH

0.5 tcyc – 15

—

Signal rise time

(all input pins

except EXTAL)

tSR

—

100

Figure 21.28

Signal fall time

(all input pins

except EXTAL)

tSF

—

100

Table 21.7 Timing of

On-Chip Supporting

Modules

656

Conditions amended

Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VREF = 3.0 V to

AVCC, VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular

specifications), Ta = –40°C to +85°C (wide-range

specifications)

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