H8SLASH3028F datasheet(40/923 Pages) RENESAS

40 / 923 page

Rev. 2.00, 09/03, page 10 of 890

Pin No.

Type

Symbol

FP-100B

TFP-100B

I/O

Name and Function

RFSH

Output

Refresh: Indicates a refresh cycle

DRAM

interface

CS2 to CS5

89, 88,

5, 4

Output

Row address strobe

RAS

RAS: Row address strobe

signal for DRAM

Output

Write enable

WE: Write enable signal for DRAM

HWR

UCAS

Output

Upper column address strobe

UCAS

UCAS: Column

address strobe signal for DRAM

LWR

LCAS

Output

Lower column address strobe

LCAS

LCAS: Column

address strobe signal for DRAM

DREQ1,

DREQ0

5, 3

Input

DMA request 1 and 0: DMAC activation

requests

DMA

controller

(DMAC)

TEND1,

TEND0

94, 93

Output

Transfer end 1 and 0: These signals indicate

that the DMAC has ended a data transfer

16-bit timer TCLKD to

TCLKA

96 to 93

Input

Clock input D to A: External clock inputs

TIOCA2 to

TIOCA0

99, 97, 95

Input/

output

Input capture/output compare A2 to A0:

GRA2 to GRA0 output compare or input capture,

or PWM output

TIOCB2 to

TIOCB0

100, 98,

Input/

output

Input capture/output compare B2 to B0:

GRB2 to GRB0 output compare or input capture,

or PWM output

8-bit timer

TMO0,

TMO2

2, 4

Output

Compare match output: Compare match

output pins

TMIO1,

TMIO3

3, 5

Input/

output

Input capture input/compare match output:

Input capture input or compare match output

pins

TCLKD to

TCLKA

96 to 93

Input

Counter external clock input: These pins input

an external clock to the counters.

Program-

mable

timing

pattern

controller

(TPC)

TP15 to TP0

9 to 2,

100 to 93

Output

TPC output 15 to 0: Pulse output

TxD2 to

TxD0

8, 13, 12

Output

Transmit data (channels 0, 1, 2): SCI data

output

RxD2 to

RxD0

9, 15, 14

Input

Receive data (channels 0, 1, 2): SCI data input

Serial com-

munication

interface

(SCI)

SCK2 to

SCK0

7, 17, 16

Input/

output

Serial clock (channels 0, 1, 2): SCI clock

input/output

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