H8SLASH3028F datasheet(11/923 Pages) RENESAS

11 / 923 page

Rev. 2.00, 09/03, page xi of xxx

Item

Page

Revision (See Manual for Details)

473

Table amended

φφφφ (MHz)

Bit

Rate

(bit/s)

Error

(%)

110

–0.02

150

0.47

13.2.8 Bit Rate

Table 13.3 Examples

of Bit Rates and BRR

Settings in

Asynchronous Mode

300

162

–0.15

600

0.47

1200

162

–0.15

2400

0.47

4800

162

–0.15

9600

0.47

15.6 Usage Notes

Table 15.5 Analog

Input Pin Ratings

556

Note amended

Note: * When conversion time = 134 states, VCC = 3.0 V to 3.6 V,

and

φ ≤ 13 MHz. For details see section 21, Electrical

Characteristics.

18.12.1 Block Diagram

Figure 18.19 ROM

Block Diagram

622

Figure amended

H'5FFFE

Even addresses

19.2.1 Connecting a

Crystal Resonator

Table 19.1(1)

Damping Resistance

Value

626

Note amended

Note: A crystal resonator between 2 MHz and 25 MHz can be

used. If the chip is to be operated at less than 2 MHz, the

on-chip frequency divider should be used. (A crystal

resonator of less than 2 MHz cannot be used.)

629

Table amended

VCC = 3.0 V to 3.6 V

Item

Symbol Min

Max

Unit

Test Conditions

tEXL

0.3

0.7

tcyc

φ ≥ 5 MHz

External clock input low

pulse width

—

φ < 5 MHz

Figure

19.6

tEXH

0.3

0.7

tcyc

φ ≥ 5 MHz

19.2.2 External Clock

Input

Table 19.3 Clock

Timing

External clock input high

pulse width

—

φ < 5 MHz

External clock rise time

tEXr

—

Figure 19.6

External clock fall time

tEXf

—5

Clock low pulse width

tCL

0.4

0.6

tcyc

φ ≥ 5 MHz

—

φ < 5 MHz

Figure

21.11

Clock high pulse width

tCH

0.4

0.6

tcyc

φ ≥ 5 MHz

—

φ < 5 MHz

External clock output

settling delay time

tDEXT*

500

—

µs

Figure 19.7

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