H8SLASH3028F datasheet(437/923 Pages) RENESAS

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H8/3028F 数据表(PDF) 437 Page - Renesas Technology Corp

部件名	H8/3028F

功能描述	Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

PDF	923 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

标志

437 / 923 page

Rev. 2.00, 09/03, page 407 of 890

10.7.7

Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode

(Cascaded Connection)

If an increment pulse occurs in the T3 state of an 8TCNT byte write cycle in 16-bit count mode,

the counter write takes priority and the byte data for which the write was performed is not

incremented. The byte data for which a write was not performed is incremented. Figure 10.24

shows the timing when an increment pulse occurs in the T2 state of a byte write to 8TCNT (upper

byte). If an increment pulse occurs in the T2 state, on the other hand, the increment takes priority.

Address bus

8TCNTH address

Internal write signal

8TCNT input clock

8TCNT (upper byte)

N+1

8TCNT write data

8TCNT (upper byte) byte write cycle

8TCNT (lower byte)

X+1

Figure 10.24 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode

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