H8SLASH3028F datasheet(446/923 Pages) RENESAS

446 / 923 page

Rev. 2.00, 09/03, page 416 of 890

11.2.3

Port B Data Direction Register (PBDDR)

PBDDR is an 8-bit write-only register that selects input or output for each pin in port B.

Bit

Initial value

Read/Write

PB0DDR

PB1DDR

PB2DDR

PB3DDR

PB4DDR

PB5DDR

PB6DDR

PB7DDR

Port B direction 7 to 0

These bits select input or

output for port B pins

Port B is multiplexed with pins TP15 to TP8. Bits corresponding to pins used for TPC output must

be set to 1. For further information about PBDDR, see section 8.12, Port B.

11.2.4

Port B Data Register (PBDR)

PBDR is an 8-bit readable/writable register that stores TPC output data for groups 2 and 3, when

these TPC output groups are used.

Bit

Initial value

Read/Write

Note: * Bits selected for TPC output by NDERB settings become read-only bits.

PB0

R/(W)*

PB1

R/(W)*

PB2

R/(W)*

PB3

R/(W)*

PB4

R/(W)*

PB5

R/(W)*

PB6

R/(W)*

PB7

R/(W)*

Port B data 7 to 0

These bits store output data

for TPC output groups 2 and 3

For further information about PBDR, see section 8.12, Port B.

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