H8SLASH3028F datasheet(600/923 Pages) RENESAS

600 / 923 page

Rev. 2.00, 09/03, page 570 of 890

17.1.2

The on-chip RAM is controlled by SYSCR. Table 17.1 gives the address and initial value of

SYSCR.

Table 17.1 System Control Register

Address*

Name

Abbreviation

R/W

Initial Value

H'EE012

System control register

SYSCR

R/W

H'09

Note: * Lower 20 bits of the address in advanced mode.

17.2

System Control Register (SYSCR)

Bit

Initial value

Read/Write

SSBY

R/W

STS2

R/W

STS1

R/W

STS0

R/W

NMIEG

R/W

SSOE

R/W

RAME

R/W

Software standby

Standby timer select 2 to 0

User bit enable

NMI edge select

Software standby

output port enable

RAM enable bit

Enables or disables

on-chip RAM

One function of SYSCR is to enable or disable access to the on-chip RAM. The on-chip RAM is

enabled or disabled by the RAME bit in SYSCR. For details about the other bits, see section 3.3,

System Control Register (SYSCR).

Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is

initialized at the rising edge of the input at the

RES pin. It is not initialized in software standby

mode.

Bit 0

RAME

Description

On-chip RAM is disabled

On-chip RAM is enabled

(Initial value)

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