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H8/3028F 数据表(PDF) 685 Page - Renesas Technology Corp |
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H8/3028F 数据表(HTML) 685 Page - Renesas Technology Corp |
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685 / 923 page  Rev. 2.00, 09/03, page 655 of 890 Condition f = 2 M to 25 MHz Item Symbol Min Max Unit Test Conditions Bus request setup time tBRQS 25 — ns Figure 21.16 Bus acknowledge delay time 1 tBACD1 —30 ns Bus acknowledge delay time 2 tBACD2 —30 ns Bus-floating time tBZD —30 ns RAS precharge time tRP 1.5 tcyc – 25 — ns CAS precharge time tCP 0.5 tcyc – 15 — ns Figure 21.17 to figure 21.19 Row address hold time tRAH 0.5 tcyc – 15 — ns RAS delay time 1 tRAD1 —25 ns RAS delay time 2 tRAD2 —30 ns CAS delay time 1 tCASD1 —25 ns CAS delay time 2 tCASD2 —25 ns WE delay time tWCD —25 ns CAS pulse width 1 tCAS1 1.5 tcyc – 20 — ns CAS pulse width 2 tCAS2 1.0 tcyc – 20 — ns CAS pulse width 3 tCAS3 1.0 tcyc – 20 — ns RAS access time tRAC — 2.5 tcyc – 40 ns Address access time tAA — 2.0 tcyc – 50 ns CAS access time tCAC — 1.5 tcyc – 50 ns WE setup time tWCS 0.5 tcyc – 20 — ns WE hold time tWCH 0.5 tcyc – 15 — ns Write data setup time tWDS 0.5 tcyc – 20 — ns WE write data hold time tWDH 0.5 tcyc – 15 — ns CAS setup time 1 tCSR1 0.5 tcyc – 20 — ns CAS setup time 2 tCSR2 0.5 tcyc – 15 — ns CAS hold time tCHR 0.5 tcyc – 15 — ns RAS pulse width tRAS 1.5 tcyc – 15 — ns Signal rise time (all input pins except EXTAL) tSR — 100 ns Figure 21.28 Signal fall time (all input pins except EXTAL) tSF — 100 ns Note: In order to secure the address hold time relative to the rise of the RD strobe, address update mode 2 should be used. For details see section 6.3.5, Address Output Method. |
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