H8SLASH3028F datasheet(782/923 Pages) RENESAS

782 / 923 page

Rev. 2.00, 09/03, page 752 of 890

B.3

Functions

Bit

Initial value

R/W:

R/W

ICIAE

R/W

ICIBE

R/W

ICICE

R/W

OCIDE

R/W

OCIAE

R/W

OCIBE

R/W

OVIE

—

Timer overflow interrupt enable

Interrupt requested by OVF flag is disabled

Interrupt requested by OVF flag is enabled

Output compare interrupt B enable

Interrupt requested by OCFB flag is disabled

Interrupt requested by OCFB flag is enabled

Output compare interrupt A enable

Interrupt requested by OCFA flag is disabled

Interrupt requested by OCFA flag is enabled

Input capture interrupt D enable

Interrupt requested by ICFD flag is disabled

Interrupt requested by ICFD flag is enabled

TIER—Timer Interrupt Enable Register

H' 90

FRT

Address to which register

is mapped*

Name of on-chip

supporting module

Names of the bits.

Dashes (—) indicate

reserved bits.

Full name of bit

Descriptions of

bit settings

Bit numbers

Initial bit values

Possible types of

access

R/W

Read only

Write only

Read and write

Note:

* When the EMC bit in BCR is cleared to 0, addresses of some registers are changed.

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