H8SLASH3028F datasheet(811/923 Pages) RENESAS

811 / 923 page

Rev. 2.00, 09/03, page 781 of 890

DTCR0A—Data Transfer Control Register 0A (cont)

H'FFF27

DMAC0

• Full address mode

Bit

Initial value

Read/Write

R/W

DTE

R/W

DTSZ

R/W

SAID

R/W

SAIDE

R/W

DTIE

R/W

DTS2A

R/W

DTS1A

R/W

DTS0A

Set both bits to 1

Data transfer select 0A

Data transfer select 2A and 1A

Normal mode

Block transfer mode

Data transfer interrupt enable

Interrupt requested by DTE bit is disabled

Interrupt requested by DTE bit is enabled

Data transfer size

Byte-size transfer

Word-size transfer

Data transfer enable

Data transfer is disabled

Data transfer is enabled

Source address increment/decrement (bit 5)

Source address increment/decrement enable (bit 4)

Bit 5

SAID

Bit 4

SAIDE

Increment/Decrement Enable

MARA is held fixed

Incremented:

If DTSZ = 0, MARA is incremented by 1 after each transfer

If DTSZ = 1, MARA is incremented by 2 after each transfer

MARA is held fixed

Decremented: If DTSZ = 0, MARA is decremented by 1 after each transfer

If DTSZ = 1, MARA is decremented by 2 after each transfer

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