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H8/3028F 数据表(PDF) 835 Page - Renesas Technology Corp |
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H8/3028F 数据表(HTML) 835 Page - Renesas Technology Corp |
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835 / 923 page  Rev. 2.00, 09/03, page 805 of 890 TCSR0—Timer Control/Status Register 0 H'FFF82 8-bit timer channel 0 Output select A1 and A0 0 Description Description Bit 1 OS1 Bit 0 OS0 ICE in TCSR1 Bit 3 OIS3 Bit 2 OIS2 1 0 1 No change at compare match A 0 output at compare match A 1 output at compare match A Output toggles at compare match A Output/input capture edge select B3 and B2 0 0 1 0 1 0 1 0 1 0 1 1 0 No change at compare match B 0 output at compare match B 1 output at compare match B Output toggles at compare match B TCORB input capture on rising edge TCORB input capture on falling edge TCORB input capture on both rising and falling edges 1 Timer overflow flag 0 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF. Bit Initial value Read/Write 0 R/(W)* 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/W 4 ADTE 0 R/W 3 OIS3 0 R/W 2 OIS2 0 R/W 1 OS1 0 R/W 0 OS0 0 1 1 [Setting condition] TCNT overflows from H'FF to H'00. Compare match flag A 0 [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA. 1 [Setting condition] TCNT = TCORA Compare match/input capture flag B 0 [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB. 1 [Setting conditions] • TCNT = TCORB • The TCNT value is transferred to TCORB by an input capture signal when TCORB functions as an input capture register. Note: * Only 0 can be written to bits 7 to 5, to clear these flags. Note: * TRGE is bit 7 of the A/D control register (ADCR). A/D trigger enable (TCSR0 only) TRGE* Bit 4 ADTE Description 0 0 A/D converter start requests by compare match A or an external trigger are disabled 1 A/D converter start requests by compare match A or an external trigger are enabled 1 0 A/D converter start requests by an external trigger are enabled 1 A/D converter start requests by compare match A are enabled |
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