H8SLASH3028F datasheet(134/923 Pages) RENESAS

134 / 923 page

Rev. 2.00, 09/03, page 104 of 890

5.4.3

Interrupt Response Time

Table 5.5 indicates the interrupt response time from the occurrence of an interrupt request until the

first instruction of the interrupt service routine is executed.

Table 5.5

Interrupt Response Time

External Memory

8-Bit Bus

16-Bit Bus

No.

Item

On-Chip

Memory

2 States

3 States

2 States

3 States

Interrupt priority

decision

Maximum number

of states until end of

current instruction

1 to 23*

1 to 27*

1 to 41*

1 to 23*

1 to 25*

Saving PC and CCR

to stack

12*

46*

Vector fetch

12*

46*

Instruction prefetch*

12*

46*

Internal processing*

Total

19 to 41

31 to 57

43 to 83

19 to 41

25 to 49

Notes: 1. 1 state for internal interrupts.

2. Prefetch after the interrupt is accepted and prefetch of the first instruction in the

interrupt service routine.

3. Internal processing after the interrupt is accepted and internal processing after vector

fetch.

4. The number of states increases if wait states are inserted in external memory access.

5. Example for DIVXS.W Rs,ERd and MULXS.W Rs,ERd

6. Example for MOV.L @(d:24,ERs),ERd and MOV.L ERs,@(d:24,ERd)

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