H8SLASH3028F datasheet(164/923 Pages) RENESAS

164 / 923 page

Rev. 2.00, 09/03, page 134 of 890

6.3.4

Chip Select Signals

For each of areas 0 to 7, the H8/3028 Group can output a chip select signal (

0 to CS7) that goes

low when the corresponding area is selected in expanded mode. Figure 6.4 shows the output

timing of a

CSn signal.

Output of

0 to CS

3: Output of CS0 to CS3 is enabled or disabled in the data direction register

(DDR) of the corresponding port.

In the expanded modes with on-chip ROM disabled, a reset leaves pin

0 in the output state and

pins

1 to CS3 in the input state. To output chip select signals CS1 to CS3, the corresponding

DDR bits must be set to 1. In the expanded modes with on-chip ROM enabled, a reset leaves pins

0 to CS3 in the input state. To output chip select signals CS0 to CS3, the corresponding DDR

bits must be set to 1. For details, see section 8, I/O Ports.

Output of

4 to CS

7: Output of CS4 to CS7 is enabled or disabled in the chip select control

4 to CS7 in the input state. To output chip select signals

4 to CS7, the corresponding CSCR bits must be set to 1. For details, see section 8, I/O Ports.

Address

External address in area n

CSn

Figure 6.4

CSn Signal Output Timing (n = 0 to 7)

When the on-chip ROM, on-chip RAM, and on-chip registers are accessed,

0 to CS7 remain

high. The

n signals are decoded from the address signals. They can be used as chip select

signals for SRAM and other devices.

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