H8SLASH3028F datasheet(229/923 Pages) RENESAS

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Rev. 2.00, 09/03, page 199 of 890

Bit 3—Data Transfer Interrupt Enable (DTIE): Enables or disables the CPU interrupt (DEND)

requested when the DTE bit is cleared to 0.

Bit 3

DTIE

Description

The DEND interrupt requested by DTE is disabled

(Initial value)

The DEND interrupt requested by DTE is enabled

Bits 2 to 0—Data Transfer Select (DTS2, DTS1, DTS0): These bits select the data transfer

activation source. Some of the selectable sources differ between channels A and B.

Bit 2

DTS2

Bit 1

DTS1

Bit 0

DTS0

Description

Compare match/input capture A interrupt from 16-bit timer channel 0

(Initial value)

Compare match/input capture A interrupt from 16-bit timer channel 1

Compare match/input capture A interrupt from 16-bit timer channel 2

Conversion-end interrupt from A/D converter

Transmit-data-empty interrupt from SCI channel 0

Receive-data-full interrupt from SCI channel 0

Falling edge of

DREQ input (channel B)

Transfer in full address mode (channel A)

Low level of

DREQ input (channel B)

Transfer in full address mode (channel A)

Note: See section 7.3.4, Data Transfer Control Registers (DTCR).

The same internal interrupt can be selected as an activation source for two or more channels at

once. In that case the channels are activated in a priority order, highest-priority channel first. For

the priority order, see section 7.4.9, Multiple-Channel Operation.

When a channel is enabled (DTE = 1), its selected DMAC activation source cannot generate a

CPU interrupt.

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