H8SLASH3028F datasheet(317/923 Pages) RENESAS

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Rev. 2.00, 09/03, page 287 of 890

8.11.2

Table 8.18 summarizes the registers of port A.

Table 8.18 Port A Registers

Initial Value

Address*

Name

R/W

Modes 1, 2, 5, 6,

and 7

Modes 3 and 4

H'EE009

Port A data direction

PADDR

H'00

H'80

H'FFFD9

Port A data register

PADR

R/W

H'00

Note: * Lower 20 bits of the address in advanced mode.

Port A Data Direction Register (PADDR): PADDR is an 8-bit write-only register that can select

input or output for each pin in port A. When pins are used for TPC output, the corresponding

PADDR bits must also be set.

PA DDR

—

Port A data direction 7 to 0

These bits select input or output for port A pins

PA DDR

Bit

Modes

3 and 4

Initial value

Read/Write

Initial value

Read/Write

Modes

1, 2, 5,

6, and 7

The pin functions that can be selected for pins PA7 to PA4 differ between modes 1, 2, 6, and 7, and

modes 3 to 5. For the method of selecting the pin functions, see tables 8.19 and 8.20.

The pin functions that can be selected for pins PA3 to PA0 are the same in modes 1 to 7. For the

method of selecting the pin functions, see table 8.21.

When port A functions as an input/output port, a pin in port A becomes an output port if the

corresponding PADDR bit is set to 1, and an input port if this bit is cleared to 0. In modes 3 and 4,

PA7DDR is fixed at 1 and PA7 functions as the A20 address output pin.

PADDR is a write-only register. Its value cannot be read. All bits return 1 when read.

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