PSD913F2 datasheet(31/91 Pages) STMICROELECTRONICS

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PSD9XX Family

PSD935G2

RESET

D 0-D 7

R/W

PAGE

PGR0

PGR1

PGR2

PGR3

DPLD

AND

GPLD

INTERNAL

SELECTS

AND LOGIC

FLASH

PLD

PGR4

PGR5

PGR6

PGR7

Figure 9. Page Register

The

PSD935G2

Functional

Blocks

(cont.)

9.1.4 Page Register

The eight bit Page Register increases the addressing capability of the microcontroller by a

factor of up to 256. The contents of the register can also be read by the microcontroller.

The outputs of the Page Register (PGR0-PGR7) are inputs to the PLD decoder and

can be included in the Flash Memory, secondary Flash memory, and SRAM chip select

equations.

If memory paging is not needed, or if not all 8 page register bits are needed for memory

paging, then these bits may be used in the PLD for general logic. See Application

Notes.

Figure 9 shows the Page Register. The eight flip flops in the register are connected to the

internal data bus D0-D7. The microcontroller can write to or read from the Page Register.

The Page Register can be accessed at address location CSIOP + E0h.

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