PSD913F2 datasheet(56/91 Pages) STMICROELECTRONICS

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PSD935G2

PSD9XX Family

9.5 Power Management

The PSD935G2 offers configurable power saving options. These options may be used

individually or in combinations, as follows:

t All memory types in a PSD (Flash, Secondary Flash, and SRAM) are built with

Zero-Power technology. In addition to using special silicon design methodology,

Zero-Power technology puts the memories into standby mode when address/data

inputs are not changing (zero DC current). As soon as a transition occurs on an input,

the affected memory “wakes up”, changes and latches its outputs, then goes back to

standby. The designer does not have to do anything special to achieve memory

standby mode when no inputs are changing—it happens automatically.

The PLD sections can also achieve standby mode when its inputs are not changing,

see PMMR registers below.

t Like the Zero-Power feature, the Automatic Power Down (APD) logic allows the PSD to

reduce to standby current automatically. The APD will block MCU address/data signals

from reaching the memories and PLDs. This feature is available on all PSD935G2

devices. The APD unit is described in more detail in section 9.5.1.

Built in logic will monitor the address strobe of the MCU for activity. If there is no

activity for a certain time period (MCU is asleep), the APD logic initiates Power Down

Mode (if enabled). Once in Power Down Mode, all address/data signals are blocked

from reaching PSD memories and PLDs, and the memories are deselected internally.

This allows the memories and PLDs to remain in standby mode even if the

address/data lines are changing state externally (noise, other devices on the MCU

bus, etc.). Keep in mind that any unblocked PLD input signals that are changing states

keeps the PLD out of standby mode, but not the memories.

t The PSD Chip Select Input (CSI) can be used to disable the internal memories,

placing them in standby mode even if inputs are changing. This feature does not block

any internal signals or disable the PLDs. This is a good alternative to using the APD

logic, especially if your MCU has a chip select output. There is a slight penalty in

memory access time when the CSI signal makes its initial transition from deselected

to selected.

t The PMMR registers can be written by the MCU at run-time to manage power. All PSD

devices support “blocking bits” in these registers that are set to block designated

signals from reaching both PLDs. Current consumption of the PLDs is directly related

to the composite frequency of the changes on their inputs (see Figures 27 and 27a).

Significant power savings can be achieved by blocking signals that are not used in

PLD logic equations at run time. PSDsoft creates a fuse map that automatically blocks

the low address byte (A7-A0) or the control signals (CNTL0-2, ALE and WRH/DBE) if

none of these signals are used in PLD logic equations.

The PSD935G2 devices have a Turbo Bit in the PMMR0 register. This bit can be set

to disable the Turbo Mode feature (default is Turbo Mode on). While Turbo Mode is

disabled, the PLDs can achieve standby current when no PLD inputs are changing

(zero DC current). Even when inputs do change, significant power can be saved at

lower frequencies (AC current), compared to when Turbo Mode is enabled. Conversely,

when the Turbo Mode is enabled, there is a significant DC current component and the

AC component is higher.

9.5.1 Automatic Power Down (APD) Unit and Power Down Mode

The APD Unit, shown in Figure 24, puts the PSD into Power Down Mode by monitoring

the activity of the address strobe (ALE/AS). If the APD unit is enabled, as soon as activity

on the address strobe stops, a four bit counter starts counting. If the address strobe

remains inactive for fifteen clock periods of the CLKIN signal, the Power Down (PDN)

signal becomes active, and the PSD will enter into Power Down Mode, discussed next.

The

PSD935G2

Functional

Blocks

(cont.)

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