PSD913F2 datasheet(35/91 Pages) STMICROELECTRONICS

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PSD9XX Family

PSD935G2

The

PSD935G2

Functional

Blocks

(cont.)

9.2.1 Decode PLD (DPLD)

The DPLD, shown in Figure 11, is used for decoding the address for internal components.

The DPLD can generate the following decode signals:

• 8 sector selects for the main Flash memory (three product terms each)

• 4 sector selects for the secondary Flash memory (three product terms each)

• 1 internal SRAM select (three product terms)

• 1 internal CSIOP select (select PSD registers, one product term)

• 1 main Flash address input (FA15, three product terms). FA15 selects the lower

or upper 32KB block in the main Flash sector. See the Memory Blocks section for

details.

Inputs to the DPLD chip selects may include address inputs, Page Register inputs and

other user defined external inputs from Ports A, B, C, D or F.

9.2.2 General Purpose PLD (GPLD)

The General Purpose PLD implements user defined system combinatorial logic function

or chip selects for external devices. Figure 12 shows how the GPLD is connected to the

I/O Ports. The GPLD has 24 outputs and each are routed to a port pin. The port pin can

also be configured as input to the GPLD. When it is not used as GPLD output or input, the

pin can be configured to perform other I/O functions.

All GPLD outputs are identical except in the number of available product terms (PDs) for

logic implementation. Select the pin that can best meet the PT requirement of your logic

function or chip select. In general, a PT is consumed for each logic “OR” function that you

specify in PSDsoft. However, certain logic functions can consume more than one PT even

if no logic “OR” is specified (such as specifying an address range with boundaries of high

granularity).

Table 13 shows the number of “native” PTs for each GPLD output pin. A native PT means

that a particular PT is dedicated to an output pin. For example, Table 13 shows that PSD

Port A pin PA0 has 3 native product terms. This means a guaranteed minimum of 3 PTs is

available to implement logic for that pin.

PSD silicon and PSDsoft can include additional PTs beyond the native PTs to implement

logic. This is a transparent operation that occurs as needed through PT expansion

(internal feedback) or PT allocation (internal borrowing). You may notice in the fitter report

generated by PSDsoft that for a given GPLD output pin, more PTs were used to implement

logic than the number of native PTs available for that pin. This is because PSDsoft has

called on unused PTs from other GPLD output pins to make your logic design fit (PT

allocation or PT expansion). For optimum results, choose a GPLD output pin with a large

number of native PTs for complicated logic.

GPLD Output on Port Pin

Number of Native

Product Terms

Port A, pins PA0-3

Port A, pins PA4-7

Port B, pins PB0-3

Port B, pins PB4-7

Port C, pins PC0-7

Table 13: GPLD Product Term Availability

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