PSD913F2 datasheet(4/91 Pages) STMICROELECTRONICS

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PSD935G2

PSD9XX Family

t A simple interface to 8-bit microcontrollers that use either multiplexed or

non-multiplexed busses. The bus interface logic uses the control signals generated by

the microcontroller automatically when the address is decoded and a read or write is

performed. A partial list of the MCU families supported include:

• Intel 8031, 80196, 80188, 80C251

• Motorola 68HC11 and 68HC16

• Philips 8031 and 80C51XA

• Zilog Z80, Z8 and Z180

• Infineon C500 family

t 4 Mbit Flash memory. This is the main Flash memory. It is divided into eight

equal-sized blocks that can be accessed with user-specified addresses.

t Internal secondary 256 Kbit Flash boot memory. It is divided into four equal-sized

blocks that can be accessed with user-specified addresses. This secondary memory

brings the ability to execute code and update the main Flash concurrently.

t 64 Kbit SRAM. The SRAM’s contents can be protected from a power failure by

connecting an external battery.

t General Purpose PLD (GPLD) with 24 outputs. The GPLD may be used to implement

external chip selects or combinatorial logic function.

t Decode PLD (DPLD) that decodes address for selection of internal memory blocks.

t 52 individually configurable I/O port pins that can be used for the following functions:

• MCU I/Os

• PLD I/Os

• Latched MCU address output

• Special function I/Os.

• I/O ports may be configured as open-drain outputs.

t Standby current as low as 50 µA for 5 V devices.

t Built-in JTAG compliant serial port allows full-chip In-System Programmability (ISP).

With it, you can program a blank device or reprogram a device in the factory or the field.

t Internal page register that can be used to expand the microcontroller address space

by a factor of 256.

t Internal programmable Power Management Unit (PMU) that supports a low power

mode called Power Down Mode. The PMU can automatically detect a lack of

microcontroller activity and put the PSD9XX into Power Down Mode.

t Erase/Write cycles:

• Flash memory – 100,000 minimum

• PLD – 1,000 minimum

2.0

Key Features

3.0 PSD9XX

Series

Part #

Flash

Main

Boot

Serial ISP

Memory

PSD9XX

I/O

PLD

Input

Output

PLD

JTAG/ISP

Kbit

SRAM

Supply

Series

Device

Pins

Inputs Macrocells Macrocells Outputs

Port

8 Sectors

(4 Sectors)

Kbit

Voltage

PSD935G2

Yes

4096

256

PSD9XX

PSD913G2

Yes

1024

256

PSD934F2

Yes

2048

256

Table 1. PSD9XX Product Matrix

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