PSD913F2 datasheet(55/91 Pages) STMICROELECTRONICS

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PSD9XX Family

PSD935G2

The

PSD935G2

Functional

Blocks

(cont.)

DATA OUT

REG.

ADDRESS

ALE

READ MUX

CONTROL REG.

DIR REG.

PLD INPUT (PORT F)

ISP OR BATTERY BACK-UP (PORT E)

DATA IN

OUTPUT

SELECT

OUTPUT

MUX

PORT PIN

DATA OUT

ADDRESS

A[ 7:0] OR A[15:8]

CONFIGURATION

BIT

Figure 23. Ports E, F and G Structure

9.4.8 Port F – Functionality and Structure

Port F can be configured to perform one or more of the following functions:

t MCU I/O Mode

t PLD Input – as direct input ot the PLD array.

t Address In – additional high address inputs. Direct input to the PLD array.

t Latched Address Out – Provide latched address out per Table 18.

t Slew Rate – pins can be set up for fast slew rate.

t Data Port – connected to D[7:0] when Port F is configured as Data Port for a

non-multiplexed bus.

9.4.9 Port G – Functionality and Structure

Port G can be configured to perform one or more of the following functions:

t MCU I/O Mode

t Latched Address Out – Provide latched address out per Table 18.

t Open Drain – pins can be configured in Open Drain Mode

PSD913F2 数据表(PDF) 55 Page - STMicroelectronics

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