PSD913F2 datasheet(6/91 Pages) STMICROELECTRONICS

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PSD935G2

PSD9XX Family

PSD9XX devices contain several major functional blocks. Figure 1 on page 3 shows the

architecture of the PSD9XX device family. The functions of each block are described

briefly in the following sections. Many of the blocks perform multiple functions and are user

configurable.

4.1 Memory

The PSD935G2 contains the following memories:

• 4 Mbit Flash

• A secondary 256 Kbit Flash memory for boot or data

• 64 Kbit SRAM.

Each of the memories is briefly discussed in the following paragraphs. A more detailed

discussion can be found in section 9.

The 4 Mbit Flash is the main memory of the PSD935G2. It is divided into eight

equally-sized sectors that are individually selectable.

The 256 Kbit secondary Flash memory is divided into four equally-sized sectors. Each

sector is individually selectable.

The 64 Kbit SRAM is intended for use as a scratchpad memory or as an extension to the

microcontroller SRAM. If an external battery is connected to the PSD9XX’s Vstby pin, data

will be retained in the event of a power failure.

Each block of memory can be located in a different address space as defined by the user.

The access times for all memory types includes the address latching and DPLD decoding

time.

4.2 PLDs

The device contains two PLD blocks, each optimized for a different function, as shown in

Table 2. The functional partitioning of the PLDs reduces power consumption, optimizes

cost/performance, and eases design entry.

The Decode PLD (DPLD) is used to decode addresses and generate chip selects for

the PSD935G2 internal memory and registers. The General Purpose PLD (GPLD) can

implement user-defined external chip selects and logic functions. The PLDs receive their

inputs from the PLD Input Bus and are differentiated by their output destinations, number

of Product Terms.

The PLDs consume minimal power by using Zero-Power design techniques. The speed

and power consumption of the PLD is controlled by the Turbo Bit in the PMMR0 register

and other bits in the PMMR2 registers. These registers are set by the microcontroller at

runtime. There is a slight penalty to PLD propagation time when invoking the non-Turbo

bit.

4.3 I/O Ports

The PSD935G2 has 52 I/O pins divided among seven ports (Port A, B, C, D, E, F and G).

Each I/O pin can be individually configured for different functions. Ports can be configured

as standard MCU I/O ports, PLD I/O, or latched address outputs for microcontrollers using

multiplexed address/data busses.

The JTAG pins can be enabled on Port E for In-System Programming (ISP). Ports F and

G can also be configured as a data port for a non-multiplexed bus.

4.4 Microcontroller Bus Interface

The PSD935G2 easily interfaces with most 8-bit microcontrollers that have either

multiplexed or non-multiplexed address/data busses. The device is configured to respond

to the microcontroller’s control signals, which are also used as inputs to the PLDs. Section

9.3.5 contains microcontroller interface examples.

4.0

PSD9XX

Architectural

Overview

Name

Abbreviation

Inputs

Outputs

Product Terms

Decode PLD

DPLD

General PLD

GPLD

136

Table 2. PLD I/O Table

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