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PSD913F2 数据表(PDF) 45 Page - STMicroelectronics

部件名 PSD913F2
功能描述  Configurable Memory System on a Chip for 8-Bit Microcontrollers
PDF  91 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

PSD913F2 数据表(HTML) 45 Page - STMicroelectronics

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PSD9XX Family
PSD935G2
44
GND
8
RESET
30
49
50
70
VCC
929
69
VCC
VCC
VCC
GND GND GND GND
A[19:12] D[7:0]
A[3:0]
3
4
5
6
7
10
11
12
13
14
15
16
17
18
19
20
59
60
40
79
80
1
2
39
71
72
73
74
75
76
77
78
A4D0
A5D1
A6D2
A7D3
A8D4
A9D5
A10D6
A11D7
A12
A13
A14
A15
A16
A17
A18
A19
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
31
32
33
34
35
36
37
38
21
22
23
24
25
26
27
28
51
52
53
54
55
56
57
58
61
62
63
64
65
66
67
68
41
42
43
44
45
46
47
48
ADIO8
ADI09
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
CNTL0 (WR)
CNTL1 (RD)
CNTL2 (PSEN)
PD0 (ALE)
PD1 (CLKIN)
PD2 (CSI)
PD3
RESET
PE0 (TMS)
PE1 (TCK/ST)
PE2 (TDI)
PE3 (TDO)
PE4 (TSTAT/RDY)
PE5 (TERR)
PE6 (VSTBY)
PE7 (VBATON)
RESET
WR
RESET
RD
A3
A2
A1
A0
VCC
PSEN
ALE
A0
A1
A2
A3
A4D0
A5D1
A6D2
A7D3
A8D4
A9D5
A10D6
A11D7
A12D8
A13D9
A14D10
A15D11
A16D12
A17D13
A18D14
A19D15
A3
A2
A1
A0/WRH
WRL
RD
PSEN
ALE
43
42
41
40
39
38
37
36
24
25
26
27
28
29
30
31
5
4
3
2
18
19
32
33
XTAL1
XTAL2
RXD0
TXD0
RXD1
TXD1
T2EX
T2
T0
RST
INT0
INT1
EA/WAIT
BUSW
21
20
11
13
6
7
9
8
16
10
14
15
35
17
CRYSTAL
XA-G3
PSD935G2
Figure 18. Interfacing the PSD935G2 to the 80C51XA, 8-Bit Data Bus



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